Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4400627 [patent_doc_number] => 06264706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Substrate processing apparatus with local exhaust for removing contaminants' [patent_app_type] => 1 [patent_app_number] => 9/510173 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/264/06264706.pdf [firstpage_image] =>[orig_patent_app_number] => 510173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510173
Substrate processing apparatus with local exhaust for removing contaminants Feb 21, 2000 Issued
Array ( [id] => 4257795 [patent_doc_number] => 06204091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method of assembling a semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/505609 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7716 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204091.pdf [firstpage_image] =>[orig_patent_app_number] => 505609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505609
Method of assembling a semiconductor chip package Feb 16, 2000 Issued
Array ( [id] => 1344185 [patent_doc_number] => 06590277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Reduced stress LOC assembly' [patent_app_type] => B1 [patent_app_number] => 09/505058 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4741 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590277.pdf [firstpage_image] =>[orig_patent_app_number] => 09505058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505058
Reduced stress LOC assembly Feb 15, 2000 Issued
Array ( [id] => 1528014 [patent_doc_number] => 06479326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Heat sink for microchip application' [patent_app_type] => B1 [patent_app_number] => 09/505391 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5726 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479326.pdf [firstpage_image] =>[orig_patent_app_number] => 09505391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505391
Heat sink for microchip application Feb 15, 2000 Issued
09/485828 PRESS CONTACT TYPE SEMICONDUCTOR DEVICE AND POWER CONVERTER USING THE SAME Feb 15, 2000 Abandoned
Array ( [id] => 4414390 [patent_doc_number] => 06224638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot' [patent_app_type] => 1 [patent_app_number] => 9/502391 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 13407 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/224/06224638.pdf [firstpage_image] =>[orig_patent_app_number] => 502391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502391
Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot Feb 9, 2000 Issued
Array ( [id] => 4358509 [patent_doc_number] => 06168974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Process of mounting spring contacts to semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/499963 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 17141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168974.pdf [firstpage_image] =>[orig_patent_app_number] => 499963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499963
Process of mounting spring contacts to semiconductor devices Feb 7, 2000 Issued
Array ( [id] => 4414348 [patent_doc_number] => 06265768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Chip scale package' [patent_app_type] => 1 [patent_app_number] => 9/494648 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2622 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265768.pdf [firstpage_image] =>[orig_patent_app_number] => 494648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494648
Chip scale package Jan 30, 2000 Issued
Array ( [id] => 1603239 [patent_doc_number] => 06433419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Face-up semiconductor chip assemblies' [patent_app_type] => B1 [patent_app_number] => 09/488268 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 20808 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433419.pdf [firstpage_image] =>[orig_patent_app_number] => 09488268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488268
Face-up semiconductor chip assemblies Jan 19, 2000 Issued
Array ( [id] => 6016468 [patent_doc_number] => 20020102832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/478508 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5990 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102832.pdf [firstpage_image] =>[orig_patent_app_number] => 09478508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478508
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jan 5, 2000 Abandoned
Array ( [id] => 7639771 [patent_doc_number] => 06396145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor device and method for manufacturing the same technical field' [patent_app_type] => B1 [patent_app_number] => 09/446979 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 7720 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396145.pdf [firstpage_image] =>[orig_patent_app_number] => 09446979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/446979
Semiconductor device and method for manufacturing the same technical field Dec 29, 1999 Issued
Array ( [id] => 4400613 [patent_doc_number] => 06264705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Processing system' [patent_app_type] => 1 [patent_app_number] => 9/472199 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/264/06264705.pdf [firstpage_image] =>[orig_patent_app_number] => 472199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472199
Processing system Dec 26, 1999 Issued
Array ( [id] => 1474502 [patent_doc_number] => RE037539 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Sealed stacked arrangement of semiconductor devices' [patent_app_type] => E1 [patent_app_number] => 09/471000 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 67 [patent_no_of_words] => 26073 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037539.pdf [firstpage_image] =>[orig_patent_app_number] => 09471000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471000
Sealed stacked arrangement of semiconductor devices Dec 22, 1999 Issued
Array ( [id] => 4347162 [patent_doc_number] => 06214630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Wafer level integrated circuit structure and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/471059 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4078 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214630.pdf [firstpage_image] =>[orig_patent_app_number] => 471059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471059
Wafer level integrated circuit structure and method of manufacturing the same Dec 21, 1999 Issued
Array ( [id] => 4333821 [patent_doc_number] => 06320248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Lead frame and method of fabricating semiconductor device including the lead frame' [patent_app_type] => 1 [patent_app_number] => 9/469078 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5335 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320248.pdf [firstpage_image] =>[orig_patent_app_number] => 469078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469078
Lead frame and method of fabricating semiconductor device including the lead frame Dec 20, 1999 Issued
Array ( [id] => 4372830 [patent_doc_number] => 06274883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Structure of a ball grid array substrate with charts for indicating position of defective chips' [patent_app_type] => 1 [patent_app_number] => 9/459490 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1019 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274883.pdf [firstpage_image] =>[orig_patent_app_number] => 459490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459490
Structure of a ball grid array substrate with charts for indicating position of defective chips Dec 12, 1999 Issued
Array ( [id] => 4270440 [patent_doc_number] => 06323045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process' [patent_app_type] => 1 [patent_app_number] => 9/456590 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323045.pdf [firstpage_image] =>[orig_patent_app_number] => 456590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456590
Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process Dec 7, 1999 Issued
Array ( [id] => 4269431 [patent_doc_number] => 06245599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate' [patent_app_type] => 1 [patent_app_number] => 9/456508 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 11222 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245599.pdf [firstpage_image] =>[orig_patent_app_number] => 456508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456508
Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate Dec 7, 1999 Issued
Array ( [id] => 1554681 [patent_doc_number] => 06348727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'High current semiconductor device package with plastic housing and conductive tab' [patent_app_type] => B1 [patent_app_number] => 09/455699 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 1214 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348727.pdf [firstpage_image] =>[orig_patent_app_number] => 09455699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455699
High current semiconductor device package with plastic housing and conductive tab Dec 6, 1999 Issued
Array ( [id] => 7604954 [patent_doc_number] => 07115976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method and apparatus for epoxy LOC die attachment' [patent_app_type] => utility [patent_app_number] => 09/455038 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5932 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115976.pdf [firstpage_image] =>[orig_patent_app_number] => 09455038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455038
Method and apparatus for epoxy LOC die attachment Dec 5, 1999 Issued
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