Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4335005 [patent_doc_number] => 06284006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Processing apparatus for microelectronic devices in which polymeric bellows are used to help accomplish substrate transport inside of the apparatus' [patent_app_type] => 1 [patent_app_number] => 9/440388 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5223 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284006.pdf [firstpage_image] =>[orig_patent_app_number] => 440388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440388
Processing apparatus for microelectronic devices in which polymeric bellows are used to help accomplish substrate transport inside of the apparatus Nov 14, 1999 Issued
09/436598 POWER SEMICONDUCTOR MODULE WITH CERAMIC SUBSTRATE Nov 8, 1999 Abandoned
Array ( [id] => 1352287 [patent_doc_number] => 06580159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Integrated circuit device packages and substrates for making the packages' [patent_app_type] => B1 [patent_app_number] => 09/434589 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 6628 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580159.pdf [firstpage_image] =>[orig_patent_app_number] => 09434589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434589
Integrated circuit device packages and substrates for making the packages Nov 4, 1999 Issued
Array ( [id] => 4224511 [patent_doc_number] => 06117193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Optical sensor array mounting and alignment' [patent_app_type] => 1 [patent_app_number] => 9/422008 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6974 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117193.pdf [firstpage_image] =>[orig_patent_app_number] => 422008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422008
Optical sensor array mounting and alignment Oct 19, 1999 Issued
Array ( [id] => 4130425 [patent_doc_number] => 06146908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method of manufacturing a test circuit on a silicon wafer' [patent_app_type] => 1 [patent_app_number] => 9/420259 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5441 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146908.pdf [firstpage_image] =>[orig_patent_app_number] => 420259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420259
Method of manufacturing a test circuit on a silicon wafer Oct 17, 1999 Issued
Array ( [id] => 4210163 [patent_doc_number] => 06078092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Resettable fuse integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 9/419308 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 1057 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078092.pdf [firstpage_image] =>[orig_patent_app_number] => 419308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419308
Resettable fuse integrated circuit package Oct 17, 1999 Issued
Array ( [id] => 1583123 [patent_doc_number] => 06358288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Touchless stabilizer for processing spherical devices' [patent_app_type] => B1 [patent_app_number] => 09/418157 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358288.pdf [firstpage_image] =>[orig_patent_app_number] => 09418157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418157
Touchless stabilizer for processing spherical devices Oct 12, 1999 Issued
Array ( [id] => 4196570 [patent_doc_number] => 06130474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Leads under chip IC package' [patent_app_type] => 1 [patent_app_number] => 9/417159 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130474.pdf [firstpage_image] =>[orig_patent_app_number] => 417159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417159
Leads under chip IC package Oct 11, 1999 Issued
Array ( [id] => 1053126 [patent_doc_number] => 06858453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Integrated circuit package alignment feature' [patent_app_type] => utility [patent_app_number] => 09/416368 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3826 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858453.pdf [firstpage_image] =>[orig_patent_app_number] => 09416368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416368
Integrated circuit package alignment feature Oct 11, 1999 Issued
Array ( [id] => 6044419 [patent_doc_number] => 20020167074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'LEAD FRAME AND BOTTOM LEAD SEMICONDUCTOR PACKAGE USING THE LEAD FRAME' [patent_app_type] => new [patent_app_number] => 09/415268 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6311 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167074.pdf [firstpage_image] =>[orig_patent_app_number] => 09415268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415268
Lead frame and bottom lead semiconductor package using the lead frame Oct 11, 1999 Issued
09/415508 METHOD AND SYSTEM FOR CONSTRUCTING SEMICONDUCTOR DEVICES Oct 7, 1999 Abandoned
Array ( [id] => 1366498 [patent_doc_number] => 06566163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method for making a contactless card with antenna connected with soldered wires' [patent_app_type] => B1 [patent_app_number] => 09/381803 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566163.pdf [firstpage_image] =>[orig_patent_app_number] => 09381803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/381803
Method for making a contactless card with antenna connected with soldered wires Sep 23, 1999 Issued
Array ( [id] => 4236532 [patent_doc_number] => 06090633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Multiple-plane pair thin-film structure and process of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/401098 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 5357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090633.pdf [firstpage_image] =>[orig_patent_app_number] => 401098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401098
Multiple-plane pair thin-film structure and process of manufacture Sep 21, 1999 Issued
Array ( [id] => 4326040 [patent_doc_number] => 06319733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of manufacturing semiconductor device, semiconductor equipment and manufacturing system' [patent_app_type] => 1 [patent_app_number] => 9/395219 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5981 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319733.pdf [firstpage_image] =>[orig_patent_app_number] => 395219 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395219
Method of manufacturing semiconductor device, semiconductor equipment and manufacturing system Sep 13, 1999 Issued
Array ( [id] => 4254934 [patent_doc_number] => 06222259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Stack package and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/393869 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2950 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222259.pdf [firstpage_image] =>[orig_patent_app_number] => 393869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393869
Stack package and method of fabricating the same Sep 9, 1999 Issued
Array ( [id] => 1155841 [patent_doc_number] => 06764938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof' [patent_app_type] => B2 [patent_app_number] => 09/392722 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 3617 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764938.pdf [firstpage_image] =>[orig_patent_app_number] => 09392722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392722
Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof Sep 8, 1999 Issued
Array ( [id] => 4414418 [patent_doc_number] => 06265775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Flip chip technique for chip assembly' [patent_app_type] => 1 [patent_app_number] => 9/392153 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265775.pdf [firstpage_image] =>[orig_patent_app_number] => 392153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392153
Flip chip technique for chip assembly Sep 7, 1999 Issued
Array ( [id] => 7636043 [patent_doc_number] => 06380617 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Electrode terminal connection structure of semiconductor module' [patent_app_type] => B1 [patent_app_number] => 09/389329 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3960 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380617.pdf [firstpage_image] =>[orig_patent_app_number] => 09389329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389329
Electrode terminal connection structure of semiconductor module Sep 2, 1999 Issued
Array ( [id] => 4424789 [patent_doc_number] => 06225687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Chip package with degassing holes' [patent_app_type] => 1 [patent_app_number] => 9/388768 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3764 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225687.pdf [firstpage_image] =>[orig_patent_app_number] => 388768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388768
Chip package with degassing holes Sep 1, 1999 Issued
Array ( [id] => 4161517 [patent_doc_number] => 06107682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Compliant wirebond packages having wire loop' [patent_app_type] => 1 [patent_app_number] => 9/387880 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 6532 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107682.pdf [firstpage_image] =>[orig_patent_app_number] => 387880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387880
Compliant wirebond packages having wire loop Aug 31, 1999 Issued
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