
David E. Graybill
Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1155841
[patent_doc_number] => 06764938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/392722
[patent_app_country] => US
[patent_app_date] => 1999-09-09
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/764/06764938.pdf
[firstpage_image] =>[orig_patent_app_number] => 09392722
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/392722 | Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof | Sep 8, 1999 | Issued |
Array
(
[id] => 4414418
[patent_doc_number] => 06265775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Flip chip technique for chip assembly'
[patent_app_type] => 1
[patent_app_number] => 9/392153
[patent_app_country] => US
[patent_app_date] => 1999-09-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/392153 | Flip chip technique for chip assembly | Sep 7, 1999 | Issued |
Array
(
[id] => 7636043
[patent_doc_number] => 06380617
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[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Electrode terminal connection structure of semiconductor module'
[patent_app_type] => B1
[patent_app_number] => 09/389329
[patent_app_country] => US
[patent_app_date] => 1999-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/380/06380617.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389329 | Electrode terminal connection structure of semiconductor module | Sep 2, 1999 | Issued |
Array
(
[id] => 4424789
[patent_doc_number] => 06225687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Chip package with degassing holes'
[patent_app_type] => 1
[patent_app_number] => 9/388768
[patent_app_country] => US
[patent_app_date] => 1999-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/225/06225687.pdf
[firstpage_image] =>[orig_patent_app_number] => 388768
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/388768 | Chip package with degassing holes | Sep 1, 1999 | Issued |
Array
(
[id] => 4161517
[patent_doc_number] => 06107682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Compliant wirebond packages having wire loop'
[patent_app_type] => 1
[patent_app_number] => 9/387880
[patent_app_country] => US
[patent_app_date] => 1999-09-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/107/06107682.pdf
[firstpage_image] =>[orig_patent_app_number] => 387880
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387880 | Compliant wirebond packages having wire loop | Aug 31, 1999 | Issued |
| 09/385959 | SEMICONDUCTOR APPARATUS AND PROCESS OF PRODUCTION THEREOF | Aug 29, 1999 | Abandoned |
Array
(
[id] => 1498596
[patent_doc_number] => 06485531
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Process chamber'
[patent_app_type] => B1
[patent_app_number] => 09/384818
[patent_app_country] => US
[patent_app_date] => 1999-08-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/485/06485531.pdf
[firstpage_image] =>[orig_patent_app_number] => 09384818
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/384818 | Process chamber | Aug 26, 1999 | Issued |
| 09/382929 | PACKAGING OF ELECTRONIC CHIPS WITH AIR BRIDGE STRUCTURES | Aug 24, 1999 | Abandoned |
Array
(
[id] => 4424826
[patent_doc_number] => 06225693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Semiconductor package for radio frequency'
[patent_app_type] => 1
[patent_app_number] => 9/377899
[patent_app_country] => US
[patent_app_date] => 1999-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/225/06225693.pdf
[firstpage_image] =>[orig_patent_app_number] => 377899
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/377899 | Semiconductor package for radio frequency | Aug 19, 1999 | Issued |
Array
(
[id] => 1175755
[patent_doc_number] => 06750488
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-15
[patent_title] => 'Focal plane plate for a high-resolution camera with light-sensitive semiconductor sensors'
[patent_app_type] => B1
[patent_app_number] => 09/376442
[patent_app_country] => US
[patent_app_date] => 1999-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/750/06750488.pdf
[firstpage_image] =>[orig_patent_app_number] => 09376442
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376442 | Focal plane plate for a high-resolution camera with light-sensitive semiconductor sensors | Aug 17, 1999 | Issued |
Array
(
[id] => 6091335
[patent_doc_number] => 20020050403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-02
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 09/370990
[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0050/20020050403.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/370990 | Semiconductor device | Aug 9, 1999 | Issued |
Array
(
[id] => 4136325
[patent_doc_number] => 06015722
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[patent_issue_date] => 2000-01-18
[patent_title] => 'Method for assembling an integrated circuit chip package having an underfill material between a chip and a substrate'
[patent_app_type] => 1
[patent_app_number] => 9/369800
[patent_app_country] => US
[patent_app_date] => 1999-08-06
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[firstpage_image] =>[orig_patent_app_number] => 369800
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/369800 | Method for assembling an integrated circuit chip package having an underfill material between a chip and a substrate | Aug 5, 1999 | Issued |
Array
(
[id] => 4106360
[patent_doc_number] => 06022762
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[patent_title] => 'Process for forming a morphological edge structure to seal integrated electronic devices'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/368559 | Process for forming a morphological edge structure to seal integrated electronic devices | Aug 4, 1999 | Issued |
Array
(
[id] => 4376775
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Array
(
[id] => 4287141
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[patent_title] => 'Wafer and transport system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/363875 | Wafer and transport system | Jul 28, 1999 | Issued |
Array
(
[id] => 4350003
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[patent_title] => 'Resin molded semiconductor device and method for manufacturing the same'
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[firstpage_image] =>[orig_patent_app_number] => 341918
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Array
(
[id] => 6973099
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[patent_title] => 'HEAT SINK FOR A SEMICONDUCTOR DEVICE'
[patent_app_type] => new-utility
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Array
(
[id] => 6671938
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[patent_title] => 'UN-PACKAGED OR SEMI-PACKAGED ELECTRICALLY TESTED ELECTRONIC DEVICE FREE FROM INFANTILE MORTALITY AND PROCESS FOR MANUFACTURE THEREOF'
[patent_app_type] => new
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Array
(
[id] => 4162546
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[patent_issue_date] => 2000-12-05
[patent_title] => 'Optical module and lead frame for optical module'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/308779 | Optical module and lead frame for optical module | Jul 8, 1999 | Issued |
Array
(
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