
David E. Graybill
Examiner (ID: 8531)
| Most Active Art Unit | 2894 |
| Art Unit(s) | 1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4195176
[patent_doc_number] => 06153926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/324799
[patent_app_country] => US
[patent_app_date] => 1999-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 5989
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/153/06153926.pdf
[firstpage_image] =>[orig_patent_app_number] => 324799
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/324799 | Semiconductor device | Jun 2, 1999 | Issued |
Array
(
[id] => 1421048
[patent_doc_number] => 06521979
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Member for semiconductor package and semiconductor package using the same, and fabrication method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/324780
[patent_app_country] => US
[patent_app_date] => 1999-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2443
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521979.pdf
[firstpage_image] =>[orig_patent_app_number] => 09324780
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/324780 | Member for semiconductor package and semiconductor package using the same, and fabrication method thereof | Jun 2, 1999 | Issued |
Array
(
[id] => 4343519
[patent_doc_number] => 06284571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Lead frame assemblies with voltage reference plane and IC packages including same'
[patent_app_type] => 1
[patent_app_number] => 9/318019
[patent_app_country] => US
[patent_app_date] => 1999-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4554
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284571.pdf
[firstpage_image] =>[orig_patent_app_number] => 318019
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/318019 | Lead frame assemblies with voltage reference plane and IC packages including same | May 24, 1999 | Issued |
Array
(
[id] => 4348864
[patent_doc_number] => 06190425
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Memory bar and related circuits and methods'
[patent_app_type] => 1
[patent_app_number] => 9/309339
[patent_app_country] => US
[patent_app_date] => 1999-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 2261
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/190/06190425.pdf
[firstpage_image] =>[orig_patent_app_number] => 309339
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/309339 | Memory bar and related circuits and methods | May 10, 1999 | Issued |
Array
(
[id] => 4137697
[patent_doc_number] => 06063140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Process for manufacturing a metallized film capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/307399
[patent_app_country] => US
[patent_app_date] => 1999-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2035
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063140.pdf
[firstpage_image] =>[orig_patent_app_number] => 307399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/307399 | Process for manufacturing a metallized film capacitor | May 6, 1999 | Issued |
Array
(
[id] => 7634868
[patent_doc_number] => 06656750
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Method for testing chips on flat solder bumps'
[patent_app_type] => B1
[patent_app_number] => 09/301889
[patent_app_country] => US
[patent_app_date] => 1999-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 3059
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/656/06656750.pdf
[firstpage_image] =>[orig_patent_app_number] => 09301889
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/301889 | Method for testing chips on flat solder bumps | Apr 28, 1999 | Issued |
Array
(
[id] => 4380703
[patent_doc_number] => 06277673
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Leads under chip in conventional IC package'
[patent_app_type] => 1
[patent_app_number] => 9/302083
[patent_app_country] => US
[patent_app_date] => 1999-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4420
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/277/06277673.pdf
[firstpage_image] =>[orig_patent_app_number] => 302083
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/302083 | Leads under chip in conventional IC package | Apr 28, 1999 | Issued |
Array
(
[id] => 4406837
[patent_doc_number] => 06238951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate'
[patent_app_type] => 1
[patent_app_number] => 9/298696
[patent_app_country] => US
[patent_app_date] => 1999-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 4023
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/238/06238951.pdf
[firstpage_image] =>[orig_patent_app_number] => 298696
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/298696 | Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate | Apr 22, 1999 | Issued |
Array
(
[id] => 1113802
[patent_doc_number] => 06803657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Gravitationally-assisted control of spread of viscous material applied to semiconductor assembly components'
[patent_app_type] => B2
[patent_app_number] => 09/295709
[patent_app_country] => US
[patent_app_date] => 1999-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 43
[patent_no_of_words] => 5484
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803657.pdf
[firstpage_image] =>[orig_patent_app_number] => 09295709
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/295709 | Gravitationally-assisted control of spread of viscous material applied to semiconductor assembly components | Apr 20, 1999 | Issued |
Array
(
[id] => 4274959
[patent_doc_number] => 06281048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Method of making an electronic component, and an electronic component'
[patent_app_type] => 1
[patent_app_number] => 9/295118
[patent_app_country] => US
[patent_app_date] => 1999-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1794
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281048.pdf
[firstpage_image] =>[orig_patent_app_number] => 295118
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/295118 | Method of making an electronic component, and an electronic component | Apr 18, 1999 | Issued |
Array
(
[id] => 1494706
[patent_doc_number] => 06403387
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Method and apparatus for transfer molding encapsulation of a semiconductor die with attached heat sink'
[patent_app_type] => B1
[patent_app_number] => 09/287665
[patent_app_country] => US
[patent_app_date] => 1999-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3048
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/403/06403387.pdf
[firstpage_image] =>[orig_patent_app_number] => 09287665
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/287665 | Method and apparatus for transfer molding encapsulation of a semiconductor die with attached heat sink | Apr 6, 1999 | Issued |
Array
(
[id] => 3993192
[patent_doc_number] => 05985684
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Process for manufacturing a laser diode having a heat sink'
[patent_app_type] => 1
[patent_app_number] => 9/286145
[patent_app_country] => US
[patent_app_date] => 1999-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 5117
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/985/05985684.pdf
[firstpage_image] =>[orig_patent_app_number] => 286145
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/286145 | Process for manufacturing a laser diode having a heat sink | Apr 4, 1999 | Issued |
Array
(
[id] => 4407958
[patent_doc_number] => 06309914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Method for making a semiconductor package'
[patent_app_type] => 1
[patent_app_number] => 9/285629
[patent_app_country] => US
[patent_app_date] => 1999-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 3701
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/309/06309914.pdf
[firstpage_image] =>[orig_patent_app_number] => 285629
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/285629 | Method for making a semiconductor package | Apr 2, 1999 | Issued |
Array
(
[id] => 4293663
[patent_doc_number] => 06184065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Photolithographically patterned spring contact'
[patent_app_type] => 1
[patent_app_number] => 9/276098
[patent_app_country] => US
[patent_app_date] => 1999-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 30
[patent_no_of_words] => 6632
[patent_no_of_claims] => 79
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/184/06184065.pdf
[firstpage_image] =>[orig_patent_app_number] => 276098
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/276098 | Photolithographically patterned spring contact | Mar 24, 1999 | Issued |
Array
(
[id] => 4243110
[patent_doc_number] => 06144104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'High-operating-temperature electronic component'
[patent_app_type] => 1
[patent_app_number] => 9/275129
[patent_app_country] => US
[patent_app_date] => 1999-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 3923
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144104.pdf
[firstpage_image] =>[orig_patent_app_number] => 275129
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/275129 | High-operating-temperature electronic component | Mar 23, 1999 | Issued |
Array
(
[id] => 7643926
[patent_doc_number] => 06429112
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Multi-layer substrates and fabrication processes'
[patent_app_type] => B1
[patent_app_number] => 09/271688
[patent_app_country] => US
[patent_app_date] => 1999-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 7537
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 10
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429112.pdf
[firstpage_image] =>[orig_patent_app_number] => 09271688
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/271688 | Multi-layer substrates and fabrication processes | Mar 17, 1999 | Issued |
Array
(
[id] => 4087032
[patent_doc_number] => 06054756
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Connection components with frangible leads and bus'
[patent_app_type] => 1
[patent_app_number] => 9/268289
[patent_app_country] => US
[patent_app_date] => 1999-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 38
[patent_no_of_words] => 14972
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054756.pdf
[firstpage_image] =>[orig_patent_app_number] => 268289
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/268289 | Connection components with frangible leads and bus | Mar 14, 1999 | Issued |
Array
(
[id] => 4400602
[patent_doc_number] => 06264704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Method and apparatus for mounting component'
[patent_app_type] => 1
[patent_app_number] => 9/266928
[patent_app_country] => US
[patent_app_date] => 1999-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 9832
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/264/06264704.pdf
[firstpage_image] =>[orig_patent_app_number] => 266928
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266928 | Method and apparatus for mounting component | Mar 11, 1999 | Issued |
| 09/261328 | ULTRA-FINE CONTACT ALIGNMENT | Mar 2, 1999 | Abandoned |
Array
(
[id] => 6573161
[patent_doc_number] => 20020014688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'CONTROLLED COLLAPSE CHIP CONNECTION (C4) INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO DISSIMILAR UNDERFILL MATERIALS'
[patent_app_type] => new
[patent_app_number] => 09/261849
[patent_app_country] => US
[patent_app_date] => 1999-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1705
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20020014688.pdf
[firstpage_image] =>[orig_patent_app_number] => 09261849
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/261849 | CONTROLLED COLLAPSE CHIP CONNECTION (C4) INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO DISSIMILAR UNDERFILL MATERIALS | Mar 2, 1999 | Abandoned |