Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7643926 [patent_doc_number] => 06429112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Multi-layer substrates and fabrication processes' [patent_app_type] => B1 [patent_app_number] => 09/271688 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429112.pdf [firstpage_image] =>[orig_patent_app_number] => 09271688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271688
Multi-layer substrates and fabrication processes Mar 17, 1999 Issued
Array ( [id] => 4087032 [patent_doc_number] => 06054756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Connection components with frangible leads and bus' [patent_app_type] => 1 [patent_app_number] => 9/268289 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 14972 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054756.pdf [firstpage_image] =>[orig_patent_app_number] => 268289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268289
Connection components with frangible leads and bus Mar 14, 1999 Issued
Array ( [id] => 4400602 [patent_doc_number] => 06264704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method and apparatus for mounting component' [patent_app_type] => 1 [patent_app_number] => 9/266928 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/264/06264704.pdf [firstpage_image] =>[orig_patent_app_number] => 266928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266928
Method and apparatus for mounting component Mar 11, 1999 Issued
Array ( [id] => 6573161 [patent_doc_number] => 20020014688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'CONTROLLED COLLAPSE CHIP CONNECTION (C4) INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO DISSIMILAR UNDERFILL MATERIALS' [patent_app_type] => new [patent_app_number] => 09/261849 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1705 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014688.pdf [firstpage_image] =>[orig_patent_app_number] => 09261849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261849
CONTROLLED COLLAPSE CHIP CONNECTION (C4) INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO DISSIMILAR UNDERFILL MATERIALS Mar 2, 1999 Abandoned
09/261328 ULTRA-FINE CONTACT ALIGNMENT Mar 2, 1999 Abandoned
Array ( [id] => 4310481 [patent_doc_number] => 06252300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Direct contact through hole type wafer structure' [patent_app_type] => 1 [patent_app_number] => 9/260218 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2383 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252300.pdf [firstpage_image] =>[orig_patent_app_number] => 260218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260218
Direct contact through hole type wafer structure Feb 28, 1999 Issued
Array ( [id] => 1168035 [patent_doc_number] => 06759738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Systems interconnected by bumps of joining material' [patent_app_type] => B1 [patent_app_number] => 09/250524 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 94 [patent_no_of_words] => 27111 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759738.pdf [firstpage_image] =>[orig_patent_app_number] => 09250524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250524
Systems interconnected by bumps of joining material Feb 15, 1999 Issued
09/242069 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Feb 7, 1999 Abandoned
Array ( [id] => 1463722 [patent_doc_number] => 06351028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Multiple die stack apparatus employing T-shaped interposer elements' [patent_app_type] => B1 [patent_app_number] => 09/247009 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3721 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351028.pdf [firstpage_image] =>[orig_patent_app_number] => 09247009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247009
Multiple die stack apparatus employing T-shaped interposer elements Feb 7, 1999 Issued
09/245848 METHOD OF FORMING SOLDER FILM Feb 7, 1999 Abandoned
Array ( [id] => 6060409 [patent_doc_number] => 20020030272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'SEMICONDUCTOR APPARATUS SUBSTRATE, SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING THEREOF AND ELECTRONIC APPARATUS' [patent_app_type] => new [patent_app_number] => 09/245288 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5366 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030272.pdf [firstpage_image] =>[orig_patent_app_number] => 09245288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245288
SEMICONDUCTOR APPARATUS SUBSTRATE, SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING THEREOF AND ELECTRONIC APPARATUS Feb 4, 1999 Abandoned
Array ( [id] => 4159762 [patent_doc_number] => 06139591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Wafer separating and cleaning apparatus and process' [patent_app_type] => 1 [patent_app_number] => 9/244049 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 32720 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/139/06139591.pdf [firstpage_image] =>[orig_patent_app_number] => 244049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244049
Wafer separating and cleaning apparatus and process Feb 3, 1999 Issued
Array ( [id] => 4424792 [patent_doc_number] => 06225688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Stacked microelectronic assembly and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/244581 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 8438 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225688.pdf [firstpage_image] =>[orig_patent_app_number] => 244581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244581
Stacked microelectronic assembly and method therefor Feb 3, 1999 Issued
Array ( [id] => 4400641 [patent_doc_number] => 06264707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Electrode for an electric double layer capacitor and process for producing it' [patent_app_type] => 1 [patent_app_number] => 9/238886 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4754 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/264/06264707.pdf [firstpage_image] =>[orig_patent_app_number] => 238886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238886
Electrode for an electric double layer capacitor and process for producing it Jan 27, 1999 Issued
Array ( [id] => 4190995 [patent_doc_number] => 06093962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'High frequency shielding case of semiconductor laser' [patent_app_type] => 1 [patent_app_number] => 9/238279 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 9485 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093962.pdf [firstpage_image] =>[orig_patent_app_number] => 238279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238279
High frequency shielding case of semiconductor laser Jan 26, 1999 Issued
Array ( [id] => 4094033 [patent_doc_number] => 06096568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Process for preparing a semiconductor device package for analysis of a die' [patent_app_type] => 1 [patent_app_number] => 9/226929 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2141 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096568.pdf [firstpage_image] =>[orig_patent_app_number] => 226929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226929
Process for preparing a semiconductor device package for analysis of a die Jan 7, 1999 Issued
Array ( [id] => 4404351 [patent_doc_number] => 06271059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Chip interconnection structure using stub terminals' [patent_app_type] => 1 [patent_app_number] => 9/225148 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 2258 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271059.pdf [firstpage_image] =>[orig_patent_app_number] => 225148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225148
Chip interconnection structure using stub terminals Jan 3, 1999 Issued
Array ( [id] => 4244446 [patent_doc_number] => 06091141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Bump chip scale semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/222226 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 4516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091141.pdf [firstpage_image] =>[orig_patent_app_number] => 222226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222226
Bump chip scale semiconductor package Dec 28, 1998 Issued
Array ( [id] => 4236544 [patent_doc_number] => 06136047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Solder bump transfer plate' [patent_app_type] => 1 [patent_app_number] => 9/222316 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 5405 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136047.pdf [firstpage_image] =>[orig_patent_app_number] => 222316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222316
Solder bump transfer plate Dec 28, 1998 Issued
Array ( [id] => 4331928 [patent_doc_number] => 06329711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Semiconductor device and mounting structure' [patent_app_type] => 1 [patent_app_number] => 9/200846 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 116 [patent_figures_cnt] => 181 [patent_no_of_words] => 30305 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329711.pdf [firstpage_image] =>[orig_patent_app_number] => 200846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200846
Semiconductor device and mounting structure Nov 29, 1998 Issued
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