Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
08/981702 SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATION THEREOF Mar 30, 1998 Abandoned
Array ( [id] => 4258639 [patent_doc_number] => 06306183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method of forming manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/043989 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2450 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306183.pdf [firstpage_image] =>[orig_patent_app_number] => 043989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/043989
Method of forming manufacturing semiconductor device Mar 29, 1998 Issued
Array ( [id] => 4131447 [patent_doc_number] => 06059846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Bonding wire height inspection device' [patent_app_type] => 1 [patent_app_number] => 9/042843 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3387 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/059/06059846.pdf [firstpage_image] =>[orig_patent_app_number] => 042843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042843
Bonding wire height inspection device Mar 16, 1998 Issued
Array ( [id] => 4238408 [patent_doc_number] => 06080651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Wire bonding method' [patent_app_type] => 1 [patent_app_number] => 9/042842 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3259 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080651.pdf [firstpage_image] =>[orig_patent_app_number] => 042842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042842
Wire bonding method Mar 16, 1998 Issued
Array ( [id] => 4111520 [patent_doc_number] => 06023096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor device having metal foil integral with sealing resin' [patent_app_type] => 1 [patent_app_number] => 9/032758 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4206 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023096.pdf [firstpage_image] =>[orig_patent_app_number] => 032758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032758
Semiconductor device having metal foil integral with sealing resin Feb 26, 1998 Issued
Array ( [id] => 4226729 [patent_doc_number] => 06143040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Substrate processing apparatus and maintenance method therefor' [patent_app_type] => 1 [patent_app_number] => 9/031950 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7520 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143040.pdf [firstpage_image] =>[orig_patent_app_number] => 031950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031950
Substrate processing apparatus and maintenance method therefor Feb 26, 1998 Issued
Array ( [id] => 4145206 [patent_doc_number] => 06063640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Semiconductor wafer testing method with probe pin contact' [patent_app_type] => 1 [patent_app_number] => 9/030349 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 82 [patent_no_of_words] => 19735 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063640.pdf [firstpage_image] =>[orig_patent_app_number] => 030349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030349
Semiconductor wafer testing method with probe pin contact Feb 24, 1998 Issued
Array ( [id] => 4101154 [patent_doc_number] => 06100108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of fabricating electronic circuit device' [patent_app_type] => 1 [patent_app_number] => 9/025107 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100108.pdf [firstpage_image] =>[orig_patent_app_number] => 025107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025107
Method of fabricating electronic circuit device Feb 16, 1998 Issued
Array ( [id] => 5921978 [patent_doc_number] => 20020115236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Methods of making compliant semiconductor chip packages' [patent_app_type] => new [patent_app_number] => 09/020647 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20020115236.pdf [firstpage_image] =>[orig_patent_app_number] => 09020647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020647
Methods of making compliant semiconductor chip packages Feb 8, 1998 Abandoned
Array ( [id] => 4227163 [patent_doc_number] => 06117367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Pastes for improved substrate dimensional control' [patent_app_type] => 1 [patent_app_number] => 9/021045 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4778 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117367.pdf [firstpage_image] =>[orig_patent_app_number] => 021045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021045
Pastes for improved substrate dimensional control Feb 8, 1998 Issued
Array ( [id] => 6573090 [patent_doc_number] => 20020014685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'ELECTRONIC COMPONENT WITH BALL BONDED PADS CONNECTED TO A PLATED LEAD FRAME' [patent_app_type] => new [patent_app_number] => 09/011039 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5924 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014685.pdf [firstpage_image] =>[orig_patent_app_number] => 09011039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/011039
ELECTRONIC COMPONENT WITH BALL BONDED PADS CONNECTED TO A PLATED LEAD FRAME Feb 5, 1998 Abandoned
09/019637 METHODS OF MAKING MICROELECTRONIC ASSEMBLIES Feb 5, 1998 Issued
Array ( [id] => 1456930 [patent_doc_number] => 06391067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-21 [patent_title] => 'Wafer processing apparatus and method, wafer convey robot, semiconductor substrate fabrication method, and semiconductor fabrication apparatus' [patent_app_type] => B2 [patent_app_number] => 09/015582 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7500 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391067.pdf [firstpage_image] =>[orig_patent_app_number] => 09015582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015582
Wafer processing apparatus and method, wafer convey robot, semiconductor substrate fabrication method, and semiconductor fabrication apparatus Jan 28, 1998 Issued
Array ( [id] => 4226560 [patent_doc_number] => 06074443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot' [patent_app_type] => 1 [patent_app_number] => 9/015726 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 13385 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074443.pdf [firstpage_image] =>[orig_patent_app_number] => 015726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015726
Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot Jan 28, 1998 Issued
Array ( [id] => 3993221 [patent_doc_number] => 05985686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Process for manufacturing vertical cavity surface emitting lasers using patterned wafer fusion and the device manufactured by the process' [patent_app_type] => 1 [patent_app_number] => 9/014778 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4084 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985686.pdf [firstpage_image] =>[orig_patent_app_number] => 014778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014778
Process for manufacturing vertical cavity surface emitting lasers using patterned wafer fusion and the device manufactured by the process Jan 27, 1998 Issued
Array ( [id] => 3924253 [patent_doc_number] => 05972053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Capacitor formed within printed circuit board' [patent_app_type] => 1 [patent_app_number] => 9/014953 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3048 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972053.pdf [firstpage_image] =>[orig_patent_app_number] => 014953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014953
Capacitor formed within printed circuit board Jan 27, 1998 Issued
Array ( [id] => 4177361 [patent_doc_number] => 06037192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure' [patent_app_type] => 1 [patent_app_number] => 9/012008 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3064 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037192.pdf [firstpage_image] =>[orig_patent_app_number] => 012008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012008
Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure Jan 21, 1998 Issued
Array ( [id] => 1225161 [patent_doc_number] => 06700184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Lead frame and semiconductor device having the same' [patent_app_type] => B1 [patent_app_number] => 09/009248 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 5418 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700184.pdf [firstpage_image] =>[orig_patent_app_number] => 09009248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009248
Lead frame and semiconductor device having the same Jan 19, 1998 Issued
09/007619 SEMICONDUCTOR CHIP CAPABLE OF SUPPRESSING CRACKS IN THE INSULATING LAYER Jan 14, 1998 Issued
Array ( [id] => 4183360 [patent_doc_number] => 06042623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Two-wafer loadlock wafer processing apparatus and loading and unloading method therefor' [patent_app_type] => 1 [patent_app_number] => 9/005862 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8736 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/042/06042623.pdf [firstpage_image] =>[orig_patent_app_number] => 005862 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005862
Two-wafer loadlock wafer processing apparatus and loading and unloading method therefor Jan 11, 1998 Issued
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