Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4087151 [patent_doc_number] => 06054764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Integrated circuit with tightly coupled passive components' [patent_app_type] => 1 [patent_app_number] => 8/992701 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2367 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054764.pdf [firstpage_image] =>[orig_patent_app_number] => 992701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992701
Integrated circuit with tightly coupled passive components Dec 16, 1997 Issued
Array ( [id] => 4086753 [patent_doc_number] => 06096100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for processing wafers and cleaning wafer-handling implements' [patent_app_type] => 1 [patent_app_number] => 8/989957 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4280 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096100.pdf [firstpage_image] =>[orig_patent_app_number] => 989957 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989957
Method for processing wafers and cleaning wafer-handling implements Dec 11, 1997 Issued
Array ( [id] => 3941277 [patent_doc_number] => 05989939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Process of manufacturing compliant wirebond packages' [patent_app_type] => 1 [patent_app_number] => 8/989368 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 6532 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989939.pdf [firstpage_image] =>[orig_patent_app_number] => 989368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989368
Process of manufacturing compliant wirebond packages Dec 11, 1997 Issued
08/988097 EXPANDABLE INTERPOSER FOR A MICROELECTRONIC PACKAGE AND METHOD THEREFOR Dec 9, 1997 Abandoned
Array ( [id] => 1579229 [patent_doc_number] => 06423102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Jig used for assembling semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 08/987054 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 7513 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423102.pdf [firstpage_image] =>[orig_patent_app_number] => 08987054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987054
Jig used for assembling semiconductor devices Dec 8, 1997 Issued
Array ( [id] => 4065087 [patent_doc_number] => 06068669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Compliant interconnect for testing a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/980466 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 5612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/068/06068669.pdf [firstpage_image] =>[orig_patent_app_number] => 980466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980466
Compliant interconnect for testing a semiconductor die Nov 27, 1997 Issued
Array ( [id] => 3968619 [patent_doc_number] => 05904505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Process for producing encapsulated semiconductor device having metal foil material covering and metal foil' [patent_app_type] => 1 [patent_app_number] => 8/977053 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6876 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904505.pdf [firstpage_image] =>[orig_patent_app_number] => 977053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977053
Process for producing encapsulated semiconductor device having metal foil material covering and metal foil Nov 24, 1997 Issued
Array ( [id] => 4198368 [patent_doc_number] => 06077321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Wet/dry substrate processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/966295 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6245 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077321.pdf [firstpage_image] =>[orig_patent_app_number] => 966295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966295
Wet/dry substrate processing apparatus Nov 6, 1997 Issued
Array ( [id] => 4120142 [patent_doc_number] => 06046496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Chip package' [patent_app_type] => 1 [patent_app_number] => 8/964091 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5645 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046496.pdf [firstpage_image] =>[orig_patent_app_number] => 964091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964091
Chip package Nov 3, 1997 Issued
08/963051 ELECTRONIC PACKAGE WITH MULTILEVEL CONNECTIONS Nov 2, 1997 Abandoned
Array ( [id] => 4097414 [patent_doc_number] => 06048741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices' [patent_app_type] => 1 [patent_app_number] => 8/962199 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3835 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048741.pdf [firstpage_image] =>[orig_patent_app_number] => 962199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962199
Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices Oct 30, 1997 Issued
Array ( [id] => 4132665 [patent_doc_number] => 06127724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Packaged microelectronic elements with enhanced thermal conduction' [patent_app_type] => 1 [patent_app_number] => 8/962988 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8266 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127724.pdf [firstpage_image] =>[orig_patent_app_number] => 962988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962988
Packaged microelectronic elements with enhanced thermal conduction Oct 30, 1997 Issued
Array ( [id] => 4317313 [patent_doc_number] => 06328768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Semiconductor device manufacturing line' [patent_app_type] => 1 [patent_app_number] => 8/958157 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2780 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/328/06328768.pdf [firstpage_image] =>[orig_patent_app_number] => 958157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958157
Semiconductor device manufacturing line Oct 26, 1997 Issued
Array ( [id] => 3990584 [patent_doc_number] => 05891745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Test and tear-away bond pad design' [patent_app_type] => 1 [patent_app_number] => 8/946403 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1570 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891745.pdf [firstpage_image] =>[orig_patent_app_number] => 946403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946403
Test and tear-away bond pad design Oct 6, 1997 Issued
08/944562 METHOD OF AND APPARATUS FOR MANUFACTURING THIN SOLAR BATTERY Oct 5, 1997 Abandoned
Array ( [id] => 4206225 [patent_doc_number] => 06027948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method to permit high temperature assembly processes for magnetically sensitive devices' [patent_app_type] => 1 [patent_app_number] => 8/940587 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2083 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027948.pdf [firstpage_image] =>[orig_patent_app_number] => 940587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940587
Method to permit high temperature assembly processes for magnetically sensitive devices Sep 29, 1997 Issued
Array ( [id] => 4180951 [patent_doc_number] => 06020219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method of packaging fragile devices with a gel medium confined by a rim member' [patent_app_type] => 1 [patent_app_number] => 8/939053 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020219.pdf [firstpage_image] =>[orig_patent_app_number] => 939053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939053
Method of packaging fragile devices with a gel medium confined by a rim member Sep 25, 1997 Issued
Array ( [id] => 4282705 [patent_doc_number] => 06281566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Plastic package for electronic devices' [patent_app_type] => 1 [patent_app_number] => 8/936401 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2038 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281566.pdf [firstpage_image] =>[orig_patent_app_number] => 936401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936401
Plastic package for electronic devices Sep 24, 1997 Issued
Array ( [id] => 3888672 [patent_doc_number] => 05834320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method of assembling a semiconductor device using a magnet' [patent_app_type] => 1 [patent_app_number] => 8/935976 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5822 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834320.pdf [firstpage_image] =>[orig_patent_app_number] => 935976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935976
Method of assembling a semiconductor device using a magnet Sep 22, 1997 Issued
Array ( [id] => 3876947 [patent_doc_number] => 05804460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Linewidth metrology of integrated circuit structures' [patent_app_type] => 1 [patent_app_number] => 8/931066 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2556 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804460.pdf [firstpage_image] =>[orig_patent_app_number] => 931066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931066
Linewidth metrology of integrated circuit structures Sep 14, 1997 Issued
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