
David E. Graybill
Examiner (ID: 8531)
| Most Active Art Unit | 2894 |
| Art Unit(s) | 1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3910441
[patent_doc_number] => 06001672
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method for transfer molding encapsulation of a semiconductor die with attached heat sink'
[patent_app_type] => 1
[patent_app_number] => 8/804911
[patent_app_country] => US
[patent_app_date] => 1997-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3007
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001672.pdf
[firstpage_image] =>[orig_patent_app_number] => 804911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/804911 | Method for transfer molding encapsulation of a semiconductor die with attached heat sink | Feb 24, 1997 | Issued |
Array
(
[id] => 4106302
[patent_doc_number] => 06022758
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Process for manufacturing solder leads on a semiconductor device package'
[patent_app_type] => 1
[patent_app_number] => 8/765473
[patent_app_country] => US
[patent_app_date] => 1997-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 36
[patent_no_of_words] => 2437
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022758.pdf
[firstpage_image] =>[orig_patent_app_number] => 765473
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/765473 | Process for manufacturing solder leads on a semiconductor device package | Feb 20, 1997 | Issued |
Array
(
[id] => 4206215
[patent_doc_number] => 06086641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Die bonder for a semiconductor producing apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/802291
[patent_app_country] => US
[patent_app_date] => 1997-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3149
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/086/06086641.pdf
[firstpage_image] =>[orig_patent_app_number] => 802291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/802291 | Die bonder for a semiconductor producing apparatus | Feb 17, 1997 | Issued |
Array
(
[id] => 3980276
[patent_doc_number] => 05910010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Semiconductor integrated circuit device, and process and apparatus for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/732215
[patent_app_country] => US
[patent_app_date] => 1997-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 135
[patent_figures_cnt] => 157
[patent_no_of_words] => 35658
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/910/05910010.pdf
[firstpage_image] =>[orig_patent_app_number] => 732215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732215 | Semiconductor integrated circuit device, and process and apparatus for manufacturing the same | Feb 17, 1997 | Issued |
Array
(
[id] => 3759680
[patent_doc_number] => 05851855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Process for manufacturing a MOS-technology power device chip and package assembly'
[patent_app_type] => 1
[patent_app_number] => 8/795697
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2188
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/851/05851855.pdf
[firstpage_image] =>[orig_patent_app_number] => 795697
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/795697 | Process for manufacturing a MOS-technology power device chip and package assembly | Feb 3, 1997 | Issued |
Array
(
[id] => 3785797
[patent_doc_number] => 05736428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Process for manufacturing a semiconductor device having a stepped encapsulated package'
[patent_app_type] => 1
[patent_app_number] => 8/789661
[patent_app_country] => US
[patent_app_date] => 1997-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 74
[patent_no_of_words] => 14790
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736428.pdf
[firstpage_image] =>[orig_patent_app_number] => 789661
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789661 | Process for manufacturing a semiconductor device having a stepped encapsulated package | Jan 26, 1997 | Issued |
Array
(
[id] => 4269296
[patent_doc_number] => 06245591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'High MTF optical coating for hybrid UFPA\'s'
[patent_app_type] => 1
[patent_app_number] => 8/788313
[patent_app_country] => US
[patent_app_date] => 1997-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2655
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/245/06245591.pdf
[firstpage_image] =>[orig_patent_app_number] => 788313
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788313 | High MTF optical coating for hybrid UFPA's | Jan 23, 1997 | Issued |
Array
(
[id] => 4247400
[patent_doc_number] => 06221753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Flip chip technique for chip assembly'
[patent_app_type] => 1
[patent_app_number] => 8/788209
[patent_app_country] => US
[patent_app_date] => 1997-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2938
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221753.pdf
[firstpage_image] =>[orig_patent_app_number] => 788209
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788209 | Flip chip technique for chip assembly | Jan 23, 1997 | Issued |
Array
(
[id] => 3924035
[patent_doc_number] => 05928390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Vertical processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/787862
[patent_app_country] => US
[patent_app_date] => 1997-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 11349
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/928/05928390.pdf
[firstpage_image] =>[orig_patent_app_number] => 787862
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/787862 | Vertical processing apparatus | Jan 22, 1997 | Issued |
Array
(
[id] => 3867136
[patent_doc_number] => 05837556
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Method of removing a component from a substrate'
[patent_app_type] => 1
[patent_app_number] => 8/778619
[patent_app_country] => US
[patent_app_date] => 1997-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3005
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/837/05837556.pdf
[firstpage_image] =>[orig_patent_app_number] => 778619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778619 | Method of removing a component from a substrate | Jan 5, 1997 | Issued |
Array
(
[id] => 1520627
[patent_doc_number] => 06413800
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Hermetic cold weld seal'
[patent_app_type] => B1
[patent_app_number] => 08/778331
[patent_app_country] => US
[patent_app_date] => 1997-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3511
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/413/06413800.pdf
[firstpage_image] =>[orig_patent_app_number] => 08778331
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778331 | Hermetic cold weld seal | Jan 1, 1997 | Issued |
Array
(
[id] => 4031245
[patent_doc_number] => 05907769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Leads under chip in conventional IC package'
[patent_app_type] => 1
[patent_app_number] => 8/774609
[patent_app_country] => US
[patent_app_date] => 1996-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4396
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/907/05907769.pdf
[firstpage_image] =>[orig_patent_app_number] => 774609
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/774609 | Leads under chip in conventional IC package | Dec 29, 1996 | Issued |
Array
(
[id] => 1399317
[patent_doc_number] => 06537905
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-25
[patent_title] => 'Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug'
[patent_app_type] => B1
[patent_app_number] => 08/778205
[patent_app_country] => US
[patent_app_date] => 1996-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 2
[patent_no_of_words] => 4139
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/537/06537905.pdf
[firstpage_image] =>[orig_patent_app_number] => 08778205
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778205 | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug | Dec 29, 1996 | Issued |
| 08/773873 | INTEGRATED CIRCUIT WITH LEAD FRAME PACKAGE HAVING INTERNAL POWER AND GROUND BUSES | Dec 26, 1996 | Abandoned |
Array
(
[id] => 3854019
[patent_doc_number] => 05795355
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Integrated micro-environment container loader apparatus having a semipermeable barrier'
[patent_app_type] => 1
[patent_app_number] => 8/773011
[patent_app_country] => US
[patent_app_date] => 1996-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 3407
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/795/05795355.pdf
[firstpage_image] =>[orig_patent_app_number] => 773011
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/773011 | Integrated micro-environment container loader apparatus having a semipermeable barrier | Dec 23, 1996 | Issued |
Array
(
[id] => 3936773
[patent_doc_number] => 05915169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Semiconductor chip scale package and method of producing such'
[patent_app_type] => 1
[patent_app_number] => 8/777927
[patent_app_country] => US
[patent_app_date] => 1996-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3900
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/915/05915169.pdf
[firstpage_image] =>[orig_patent_app_number] => 777927
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777927 | Semiconductor chip scale package and method of producing such | Dec 22, 1996 | Issued |
Array
(
[id] => 4180979
[patent_doc_number] => 06020221
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Process for manufacturing a semiconductor device having a stiffener member'
[patent_app_type] => 1
[patent_app_number] => 8/764039
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 8
[patent_no_of_words] => 2862
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020221.pdf
[firstpage_image] =>[orig_patent_app_number] => 764039
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764039 | Process for manufacturing a semiconductor device having a stiffener member | Dec 11, 1996 | Issued |
Array
(
[id] => 4000339
[patent_doc_number] => 05858815
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Semiconductor package and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/763605
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 32
[patent_no_of_words] => 4900
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/858/05858815.pdf
[firstpage_image] =>[orig_patent_app_number] => 763605
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763605 | Semiconductor package and method for fabricating the same | Dec 10, 1996 | Issued |
Array
(
[id] => 4090787
[patent_doc_number] => 06044534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Semiconductor device manufacturing machine and method for manufacturing a semiconductor device by using the same manufacturing machine'
[patent_app_type] => 1
[patent_app_number] => 8/761833
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 8768
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044534.pdf
[firstpage_image] =>[orig_patent_app_number] => 761833
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761833 | Semiconductor device manufacturing machine and method for manufacturing a semiconductor device by using the same manufacturing machine | Dec 8, 1996 | Issued |
Array
(
[id] => 3884118
[patent_doc_number] => 05776786
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Method for wire-bonding a covered wire'
[patent_app_type] => 1
[patent_app_number] => 8/759229
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 3133
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/776/05776786.pdf
[firstpage_image] =>[orig_patent_app_number] => 759229
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759229 | Method for wire-bonding a covered wire | Dec 4, 1996 | Issued |