
David E. Graybill
Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3885834
[patent_doc_number] => 05893727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Method for manufacturing a massive parallel interconnection attachment using flexible circuit'
[patent_app_type] => 1
[patent_app_number] => 8/689629
[patent_app_country] => US
[patent_app_date] => 1996-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2132
[patent_no_of_claims] => 6
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[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/893/05893727.pdf
[firstpage_image] =>[orig_patent_app_number] => 689629
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/689629 | Method for manufacturing a massive parallel interconnection attachment using flexible circuit | Aug 12, 1996 | Issued |
Array
(
[id] => 3939120
[patent_doc_number] => 05939773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Semiconductor laser package including a lead frame and plastic resin housing'
[patent_app_type] => 1
[patent_app_number] => 8/692355
[patent_app_country] => US
[patent_app_date] => 1996-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 4776
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[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
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[pdf_file] => patents/05/939/05939773.pdf
[firstpage_image] =>[orig_patent_app_number] => 692355
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/692355 | Semiconductor laser package including a lead frame and plastic resin housing | Aug 4, 1996 | Issued |
| 08/681599 | TWO-POLE SMT MINIATURE HOUSING FOR SEMICONDUCTOR COMPONENTS AND METHOD FOR THE MANUFACTURE THEREOF | Jul 28, 1996 | Abandoned |
Array
(
[id] => 4046234
[patent_doc_number] => 05869357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Metallization and wire bonding process for manufacturing power semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/681621
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2198
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 331
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[pdf_file] => patents/05/869/05869357.pdf
[firstpage_image] =>[orig_patent_app_number] => 681621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/681621 | Metallization and wire bonding process for manufacturing power semiconductor devices | Jul 28, 1996 | Issued |
Array
(
[id] => 4118861
[patent_doc_number] => 06120301
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/686503
[patent_app_country] => US
[patent_app_date] => 1996-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 7865
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/120/06120301.pdf
[firstpage_image] =>[orig_patent_app_number] => 686503
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/686503 | Semiconductor device and method of manufacturing the same | Jul 23, 1996 | Issued |
Array
(
[id] => 5776854
[patent_doc_number] => 20060105494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'METHOD AND APPARATUS FOR CLEANING AND SEALING DISPLAY PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 08/687117
[patent_app_country] => US
[patent_app_date] => 1996-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3442
[patent_no_of_claims] => 32
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20060105494.pdf
[firstpage_image] =>[orig_patent_app_number] => 08687117
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/687117 | METHOD AND APPARATUS FOR CLEANING AND SEALING DISPLAY PACKAGES | Jul 22, 1996 | Abandoned |
Array
(
[id] => 4250109
[patent_doc_number] => 06203582
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Modular semiconductor workpiece processing tool'
[patent_app_type] => 1
[patent_app_number] => 8/680068
[patent_app_country] => US
[patent_app_date] => 1996-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 51
[patent_no_of_words] => 26360
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/203/06203582.pdf
[firstpage_image] =>[orig_patent_app_number] => 680068
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/680068 | Modular semiconductor workpiece processing tool | Jul 14, 1996 | Issued |
Array
(
[id] => 1193807
[patent_doc_number] => 06730991
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => 'Integrated circuit chip package'
[patent_app_type] => B1
[patent_app_number] => 08/661539
[patent_app_country] => US
[patent_app_date] => 1996-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 3749
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 290
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/730/06730991.pdf
[firstpage_image] =>[orig_patent_app_number] => 08661539
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/661539 | Integrated circuit chip package | Jun 10, 1996 | Issued |
Array
(
[id] => 4026659
[patent_doc_number] => 05942012
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Heat treatment apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/663030
[patent_app_country] => US
[patent_app_date] => 1996-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 8584
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 242
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/942/05942012.pdf
[firstpage_image] =>[orig_patent_app_number] => 663030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/663030 | Heat treatment apparatus | Jun 6, 1996 | Issued |
Array
(
[id] => 4327217
[patent_doc_number] => 06319810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method for forming solder bumps'
[patent_app_type] => 1
[patent_app_number] => 8/659356
[patent_app_country] => US
[patent_app_date] => 1996-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 10605
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319810.pdf
[firstpage_image] =>[orig_patent_app_number] => 659356
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659356 | Method for forming solder bumps | Jun 5, 1996 | Issued |
Array
(
[id] => 3932208
[patent_doc_number] => 05976198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Substrate transfer and bath apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/659687
[patent_app_country] => US
[patent_app_date] => 1996-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 36
[patent_no_of_words] => 15991
[patent_no_of_claims] => 44
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/976/05976198.pdf
[firstpage_image] =>[orig_patent_app_number] => 659687
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659687 | Substrate transfer and bath apparatus | Jun 5, 1996 | Issued |
Array
(
[id] => 3858488
[patent_doc_number] => 05792676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Method of fabricating power semiconductor device and lead frame'
[patent_app_type] => 1
[patent_app_number] => 8/658611
[patent_app_country] => US
[patent_app_date] => 1996-06-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/792/05792676.pdf
[firstpage_image] =>[orig_patent_app_number] => 658611
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/658611 | Method of fabricating power semiconductor device and lead frame | Jun 4, 1996 | Issued |
Array
(
[id] => 3854034
[patent_doc_number] => 05795356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Microelectronic component fabrication facility, and process for making and using the facility'
[patent_app_type] => 1
[patent_app_number] => 8/655958
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[patent_app_date] => 1996-05-31
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[pdf_file] => patents/05/795/05795356.pdf
[firstpage_image] =>[orig_patent_app_number] => 655958
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655958 | Microelectronic component fabrication facility, and process for making and using the facility | May 30, 1996 | Issued |
Array
(
[id] => 4233986
[patent_doc_number] => 06074925
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Method for fabricating semiconductor device with polycide structure for electrode or interconnect'
[patent_app_type] => 1
[patent_app_number] => 8/653327
[patent_app_country] => US
[patent_app_date] => 1996-05-24
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[pdf_file] => patents/06/074/06074925.pdf
[firstpage_image] =>[orig_patent_app_number] => 653327
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653327 | Method for fabricating semiconductor device with polycide structure for electrode or interconnect | May 23, 1996 | Issued |
Array
(
[id] => 4031497
[patent_doc_number] => 05907786
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[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Process for manufacturing a flip-chip integrated circuit'
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[patent_app_country] => US
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[pdf_file] => patents/05/907/05907786.pdf
[firstpage_image] =>[orig_patent_app_number] => 650969
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650969 | Process for manufacturing a flip-chip integrated circuit | May 20, 1996 | Issued |
Array
(
[id] => 1378350
[patent_doc_number] => 06555399
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Double-packaged multichip semiconductor module'
[patent_app_type] => B1
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[firstpage_image] =>[orig_patent_app_number] => 08650894
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650894 | Double-packaged multichip semiconductor module | May 16, 1996 | Issued |
Array
(
[id] => 3686921
[patent_doc_number] => 05696029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Process for manufacturing a lead frame'
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[patent_app_number] => 8/665062
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[pdf_file] => patents/05/696/05696029.pdf
[firstpage_image] =>[orig_patent_app_number] => 665062
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665062 | Process for manufacturing a lead frame | May 14, 1996 | Issued |
| 08/646774 | SEMICONDUCTOR MODULAR MANUFACTURING SYSTEM | May 7, 1996 | Abandoned |
Array
(
[id] => 3760252
[patent_doc_number] => 05851894
[patent_country] => US
[patent_kind] => NA
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[patent_title] => 'Method of vertically integrating microelectronic systems'
[patent_app_type] => 1
[patent_app_number] => 8/642047
[patent_app_country] => US
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[pdf_file] => patents/05/851/05851894.pdf
[firstpage_image] =>[orig_patent_app_number] => 642047
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/642047 | Method of vertically integrating microelectronic systems | May 2, 1996 | Issued |
Array
(
[id] => 3849055
[patent_doc_number] => 05766978
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Process for testing an integrated circuit package using an integrated circuit package retainer'
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[pdf_file] => patents/05/766/05766978.pdf
[firstpage_image] =>[orig_patent_app_number] => 641243
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/641243 | Process for testing an integrated circuit package using an integrated circuit package retainer | Apr 29, 1996 | Issued |