Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4063608 [patent_doc_number] => 06008071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of forming solder bumps onto an integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/649837 [patent_app_country] => US [patent_app_date] => 1996-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 5401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008071.pdf [firstpage_image] =>[orig_patent_app_number] => 649837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649837
Method of forming solder bumps onto an integrated circuit device Apr 29, 1996 Issued
Array ( [id] => 3909203 [patent_doc_number] => 05898211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Laser diode package with heat sink' [patent_app_type] => 1 [patent_app_number] => 8/641235 [patent_app_country] => US [patent_app_date] => 1996-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5118 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898211.pdf [firstpage_image] =>[orig_patent_app_number] => 641235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641235
Laser diode package with heat sink Apr 29, 1996 Issued
Array ( [id] => 3723338 [patent_doc_number] => 05681757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Process for dispensing semiconductor die-bond adhesive using a printhead having a microjet array and the product produced by the process' [patent_app_type] => 1 [patent_app_number] => 8/639435 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6746 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681757.pdf [firstpage_image] =>[orig_patent_app_number] => 639435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639435
Process for dispensing semiconductor die-bond adhesive using a printhead having a microjet array and the product produced by the process Apr 28, 1996 Issued
Array ( [id] => 3805834 [patent_doc_number] => 05854087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method of manufacturing an optical semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/638873 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854087.pdf [firstpage_image] =>[orig_patent_app_number] => 638873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638873
Method of manufacturing an optical semiconductor device Apr 28, 1996 Issued
Array ( [id] => 3855772 [patent_doc_number] => 05705425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Process for manufacturing semiconductor devices separated by an air-bridge' [patent_app_type] => 1 [patent_app_number] => 8/638200 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5078 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705425.pdf [firstpage_image] =>[orig_patent_app_number] => 638200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638200
Process for manufacturing semiconductor devices separated by an air-bridge Apr 25, 1996 Issued
Array ( [id] => 4292221 [patent_doc_number] => 06268616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Electrical wiring board and method for identifying same' [patent_app_type] => 1 [patent_app_number] => 8/639323 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2101 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268616.pdf [firstpage_image] =>[orig_patent_app_number] => 639323 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639323
Electrical wiring board and method for identifying same Apr 24, 1996 Issued
Array ( [id] => 3836467 [patent_doc_number] => 05846853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Process for bonding circuit substrates using conductive particles and back side exposure' [patent_app_type] => 1 [patent_app_number] => 8/636915 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 29 [patent_no_of_words] => 4669 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846853.pdf [firstpage_image] =>[orig_patent_app_number] => 636915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636915
Process for bonding circuit substrates using conductive particles and back side exposure Apr 23, 1996 Issued
Array ( [id] => 3942032 [patent_doc_number] => 05989993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for galvanic forming of bonding pads' [patent_app_type] => 1 [patent_app_number] => 8/636163 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1481 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989993.pdf [firstpage_image] =>[orig_patent_app_number] => 636163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636163
Method for galvanic forming of bonding pads Apr 21, 1996 Issued
Array ( [id] => 3723604 [patent_doc_number] => 05681777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Process for manufacturing a multi-layer tab tape semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/625641 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 12520 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681777.pdf [firstpage_image] =>[orig_patent_app_number] => 625641 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625641
Process for manufacturing a multi-layer tab tape semiconductor device Mar 28, 1996 Issued
Array ( [id] => 1571230 [patent_doc_number] => 06498396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Semiconductor chip scale package and ball grid array structures' [patent_app_type] => B1 [patent_app_number] => 08/623082 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 12318 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498396.pdf [firstpage_image] =>[orig_patent_app_number] => 08623082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623082
Semiconductor chip scale package and ball grid array structures Mar 27, 1996 Issued
Array ( [id] => 3620153 [patent_doc_number] => 05688721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => '3D stack of IC chips having leads reached by vias through passivation covering access plane' [patent_app_type] => 1 [patent_app_number] => 8/622671 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 7053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688721.pdf [firstpage_image] =>[orig_patent_app_number] => 622671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622671
3D stack of IC chips having leads reached by vias through passivation covering access plane Mar 25, 1996 Issued
08/616968 INTEGRATED CIRCUIT WITH LEAD FRAME PACKAGE HAVING INTERNAL POWER AND GROUND BUSSES Mar 17, 1996 Abandoned
08/615435 CAPACITOR, METHOD FOR PRODUCING SAME AND METHOD FOR PRODUCING DIELECTRIC BODY Mar 13, 1996 Abandoned
Array ( [id] => 4141445 [patent_doc_number] => 06030857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method for application of spray adhesive to a leadframe for chip bonding' [patent_app_type] => 1 [patent_app_number] => 8/613835 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030857.pdf [firstpage_image] =>[orig_patent_app_number] => 613835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613835
Method for application of spray adhesive to a leadframe for chip bonding Mar 10, 1996 Issued
08/553495 PROCESS FOR PRODUCING A SEALING AND A MECHANICAL STRENGTH CORD BETWEEN A SUBSTRATE AND A CHIP HYBRIDIZED BY BUMPS ON THE SUBSTRATE Mar 3, 1996 Abandoned
Array ( [id] => 3908054 [patent_doc_number] => 05987722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Apparatus for transporting lead frames' [patent_app_type] => 1 [patent_app_number] => 8/608249 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 7389 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987722.pdf [firstpage_image] =>[orig_patent_app_number] => 608249 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608249
Apparatus for transporting lead frames Feb 27, 1996 Issued
Array ( [id] => 4130689 [patent_doc_number] => 06121062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Process of fabricating semiconductor unit employing bumps to bond two components' [patent_app_type] => 1 [patent_app_number] => 8/606503 [patent_app_country] => US [patent_app_date] => 1996-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3348 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121062.pdf [firstpage_image] =>[orig_patent_app_number] => 606503 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606503
Process of fabricating semiconductor unit employing bumps to bond two components Feb 22, 1996 Issued
Array ( [id] => 3687236 [patent_doc_number] => 05643835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs' [patent_app_type] => 1 [patent_app_number] => 8/602896 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3902 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643835.pdf [firstpage_image] =>[orig_patent_app_number] => 602896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/602896
Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs Feb 15, 1996 Issued
08/602179 CHIP-SCALE CARRIER AND METHODS OF MOUNTING SPRING CONTACTS TO SEMICONDUCTOR DEVICES Feb 14, 1996 Abandoned
Array ( [id] => 3759638 [patent_doc_number] => 05851852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Die attached process for SiC' [patent_app_type] => 1 [patent_app_number] => 8/600777 [patent_app_country] => US [patent_app_date] => 1996-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1319 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851852.pdf [firstpage_image] =>[orig_patent_app_number] => 600777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600777
Die attached process for SiC Feb 12, 1996 Issued
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