
David E. Graybill
Examiner (ID: 353, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2812, 2814, 1107, 2822, 3727, 2827, 1763, 2894 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11760272
[patent_doc_number] => 20170207141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'Packaged microelectronic elements having blind vias for heat dissipation'
[patent_app_type] => utility
[patent_app_number] => 15/477330
[patent_app_country] => US
[patent_app_date] => 2017-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10977
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477330
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/477330 | Packaged microelectronic elements having blind vias for heat dissipation | Apr 2, 2017 | Abandoned |
Array
(
[id] => 11974608
[patent_doc_number] => 20170278762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-28
[patent_title] => 'Redirecting solder material to visually inspectable package surface'
[patent_app_type] => utility
[patent_app_number] => 15/468045
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13115
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468045
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/468045 | Redirecting solder material to visually inspectable package surface | Mar 22, 2017 | Abandoned |
Array
(
[id] => 12263696
[patent_doc_number] => 20180082892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/467425
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6442
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467425
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/467425 | Semiconductor device and manufacturing method thereof | Mar 22, 2017 | Issued |
Array
(
[id] => 11974556
[patent_doc_number] => 20170278711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-28
[patent_title] => 'IMPURITY DIFFUSION AGENT COMPOSITION AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 15/467586
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7260
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467586
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/467586 | Impurity diffusion agent composition and method for manufacturing semiconductor substrate | Mar 22, 2017 | Issued |
Array
(
[id] => 12147584
[patent_doc_number] => 09881842
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-30
[patent_title] => 'Wimpy and nominal semiconductor device structures for vertical finFETs'
[patent_app_type] => utility
[patent_app_number] => 15/466976
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466976
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/466976 | Wimpy and nominal semiconductor device structures for vertical finFETs | Mar 22, 2017 | Issued |
Array
(
[id] => 13451767
[patent_doc_number] => 20180277426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => METHODS OF FORMING CONDUCTIVE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 15/467628
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467628
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/467628 | METHODS OF FORMING CONDUCTIVE STRUCTURES | Mar 22, 2017 | Abandoned |
Array
(
[id] => 14063845
[patent_doc_number] => 10236224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => Apparatus and method for reducing wafer warpage
[patent_app_type] => utility
[patent_app_number] => 15/467342
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 6894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467342
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/467342 | Apparatus and method for reducing wafer warpage | Mar 22, 2017 | Issued |
Array
(
[id] => 14312445
[patent_doc_number] => 20190145926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => WAFER LEVEL GATE MODULATION ENHANCED DETECTORS
[patent_app_type] => utility
[patent_app_number] => 16/097481
[patent_app_country] => US
[patent_app_date] => 2017-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5463
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097481
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/097481 | WAFER LEVEL GATE MODULATION ENHANCED DETECTORS | Mar 20, 2017 | Abandoned |
Array
(
[id] => 14801089
[patent_doc_number] => 10403554
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-03
[patent_title] => Method for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/437472
[patent_app_country] => US
[patent_app_date] => 2017-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 38
[patent_no_of_words] => 11585
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437472
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/437472 | Method for manufacturing semiconductor device | Feb 20, 2017 | Issued |
Array
(
[id] => 11623449
[patent_doc_number] => 20170133638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'METHOD FOR MANUFACTURING MEMBER HAVING IRREGULAR PATTERN'
[patent_app_type] => utility
[patent_app_number] => 15/415349
[patent_app_country] => US
[patent_app_date] => 2017-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 28145
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15415349
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/415349 | METHOD FOR MANUFACTURING MEMBER HAVING IRREGULAR PATTERN | Jan 24, 2017 | Abandoned |
Array
(
[id] => 16132697
[patent_doc_number] => 10700116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Rear-surface-incident solid state imaging element and method for manufacturing same
[patent_app_type] => utility
[patent_app_number] => 16/069342
[patent_app_country] => US
[patent_app_date] => 2016-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9727
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16069342
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/069342 | Rear-surface-incident solid state imaging element and method for manufacturing same | Dec 27, 2016 | Issued |
Array
(
[id] => 11694624
[patent_doc_number] => 20170170341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/388534
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 5859
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388534
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/388534 | INTEGRATED CIRCUIT DEVICE | Dec 21, 2016 | Abandoned |
Array
(
[id] => 13799815
[patent_doc_number] => 20190013446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-10
[patent_title] => WIDE COLOR GAMUT LIGHT-EMITTING ELEMENT
[patent_app_type] => utility
[patent_app_number] => 16/066401
[patent_app_country] => US
[patent_app_date] => 2016-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16066401
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/066401 | WIDE COLOR GAMUT LIGHT-EMITTING ELEMENT | Dec 15, 2016 | Abandoned |
Array
(
[id] => 12668746
[patent_doc_number] => 20180114748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => SUBSTRATE INTERCONNECTIONS FOR PACKAGED SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/381058
[patent_app_country] => US
[patent_app_date] => 2016-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3644
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15381058
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/381058 | Substrate interconnections for packaged semiconductor device | Dec 14, 2016 | Issued |
Array
(
[id] => 11710722
[patent_doc_number] => 20170179221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/381100
[patent_app_country] => US
[patent_app_date] => 2016-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9540
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15381100
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/381100 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME | Dec 14, 2016 | Abandoned |
Array
(
[id] => 12516177
[patent_doc_number] => 10002860
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Integrated circuit and standard cell library
[patent_app_type] => utility
[patent_app_number] => 15/380770
[patent_app_country] => US
[patent_app_date] => 2016-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7581
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380770
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/380770 | Integrated circuit and standard cell library | Dec 14, 2016 | Issued |
Array
(
[id] => 13724091
[patent_doc_number] => 20170373001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => LOW-DISPERSION COMPONENT IN AN ELECTRONIC CHIP
[patent_app_type] => utility
[patent_app_number] => 15/380894
[patent_app_country] => US
[patent_app_date] => 2016-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2561
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380894
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/380894 | Low-dispersion component in an electronic chip | Dec 14, 2016 | Issued |
Array
(
[id] => 12824161
[patent_doc_number] => 20180166559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-14
[patent_title] => METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/376916
[patent_app_country] => US
[patent_app_date] => 2016-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11244
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376916
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/376916 | METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY | Dec 12, 2016 | Abandoned |
Array
(
[id] => 15519295
[patent_doc_number] => 10566242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Minimization of plasma doping induced fin height loss
[patent_app_type] => utility
[patent_app_number] => 15/376719
[patent_app_country] => US
[patent_app_date] => 2016-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 7193
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376719
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/376719 | Minimization of plasma doping induced fin height loss | Dec 12, 2016 | Issued |
Array
(
[id] => 12314277
[patent_doc_number] => 09941144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-10
[patent_title] => Substrate breakage detection in a thermal processing system
[patent_app_type] => utility
[patent_app_number] => 15/377032
[patent_app_country] => US
[patent_app_date] => 2016-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 7482
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/377032 | Substrate breakage detection in a thermal processing system | Dec 12, 2016 | Issued |