Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3607822 [patent_doc_number] => 05589402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Process for manufacturing a package for mating with a bare semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/550416 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589402.pdf [firstpage_image] =>[orig_patent_app_number] => 550416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550416
Process for manufacturing a package for mating with a bare semiconductor die Oct 29, 1995 Issued
Array ( [id] => 4369669 [patent_doc_number] => 06287985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Process for applying a molten droplet coating for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/549350 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2416 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287985.pdf [firstpage_image] =>[orig_patent_app_number] => 549350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549350
Process for applying a molten droplet coating for integrated circuits Oct 26, 1995 Issued
Array ( [id] => 3926530 [patent_doc_number] => 05877093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Process for coating an integrated circuit device with a molten spray' [patent_app_type] => 1 [patent_app_number] => 8/549351 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3144 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877093.pdf [firstpage_image] =>[orig_patent_app_number] => 549351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549351
Process for coating an integrated circuit device with a molten spray Oct 26, 1995 Issued
Array ( [id] => 3768071 [patent_doc_number] => 05817156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Substrate heat treatment table apparatus' [patent_app_type] => 1 [patent_app_number] => 8/548151 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6437 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817156.pdf [firstpage_image] =>[orig_patent_app_number] => 548151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548151
Substrate heat treatment table apparatus Oct 24, 1995 Issued
Array ( [id] => 3687181 [patent_doc_number] => 05643831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/547532 [patent_app_country] => US [patent_app_date] => 1995-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 4119 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643831.pdf [firstpage_image] =>[orig_patent_app_number] => 547532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547532
Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device Oct 23, 1995 Issued
Array ( [id] => 4226545 [patent_doc_number] => 06074442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of separating slice base mounting member from wafer and jig adapted therefor' [patent_app_type] => 1 [patent_app_number] => 8/547107 [patent_app_country] => US [patent_app_date] => 1995-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6226 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074442.pdf [firstpage_image] =>[orig_patent_app_number] => 547107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547107
Method of separating slice base mounting member from wafer and jig adapted therefor Oct 22, 1995 Issued
Array ( [id] => 3731278 [patent_doc_number] => 05665651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Process for encapsulating a semiconductor device and lead frame' [patent_app_type] => 1 [patent_app_number] => 8/545179 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5867 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665651.pdf [firstpage_image] =>[orig_patent_app_number] => 545179 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545179
Process for encapsulating a semiconductor device and lead frame Oct 18, 1995 Issued
08/544395 METHOD OF AND APPARATUS FOR MANUFACTURING THIN SOLAR BATTERY Oct 16, 1995 Abandoned
Array ( [id] => 3866287 [patent_doc_number] => 05824119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Process for immersing a substrate in a plurality of processing baths' [patent_app_type] => 1 [patent_app_number] => 8/539202 [patent_app_country] => US [patent_app_date] => 1995-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 50 [patent_no_of_words] => 15583 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824119.pdf [firstpage_image] =>[orig_patent_app_number] => 539202 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539202
Process for immersing a substrate in a plurality of processing baths Oct 3, 1995 Issued
Array ( [id] => 3896231 [patent_doc_number] => 05897337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Process for adhesively bonding a semiconductor chip to a carrier film' [patent_app_type] => 1 [patent_app_number] => 8/533205 [patent_app_country] => US [patent_app_date] => 1995-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 54 [patent_no_of_words] => 8927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897337.pdf [firstpage_image] =>[orig_patent_app_number] => 533205 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533205
Process for adhesively bonding a semiconductor chip to a carrier film Sep 24, 1995 Issued
Array ( [id] => 3941913 [patent_doc_number] => 05946553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Process for manufacturing a semiconductor package with bi-substrate die' [patent_app_type] => 1 [patent_app_number] => 8/533373 [patent_app_country] => US [patent_app_date] => 1995-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 19 [patent_no_of_words] => 5562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946553.pdf [firstpage_image] =>[orig_patent_app_number] => 533373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533373
Process for manufacturing a semiconductor package with bi-substrate die Sep 24, 1995 Issued
Array ( [id] => 3771560 [patent_doc_number] => 05807766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Process for attaching a silicon chip to a circuit board using a block of encapsulated wires and the block of wires manufactured by the process' [patent_app_type] => 1 [patent_app_number] => 8/531814 [patent_app_country] => US [patent_app_date] => 1995-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2236 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/807/05807766.pdf [firstpage_image] =>[orig_patent_app_number] => 531814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/531814
Process for attaching a silicon chip to a circuit board using a block of encapsulated wires and the block of wires manufactured by the process Sep 20, 1995 Issued
Array ( [id] => 3824666 [patent_doc_number] => 05731243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Method of cleaning residue on a semiconductor wafer bonding pad' [patent_app_type] => 1 [patent_app_number] => 8/523775 [patent_app_country] => US [patent_app_date] => 1995-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2322 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731243.pdf [firstpage_image] =>[orig_patent_app_number] => 523775 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523775
Method of cleaning residue on a semiconductor wafer bonding pad Sep 4, 1995 Issued
Array ( [id] => 3735296 [patent_doc_number] => 05716218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Process for manufacturing an interconnect for testing a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/524018 [patent_app_country] => US [patent_app_date] => 1995-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 5614 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716218.pdf [firstpage_image] =>[orig_patent_app_number] => 524018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/524018
Process for manufacturing an interconnect for testing a semiconductor die Sep 4, 1995 Issued
Array ( [id] => 3694280 [patent_doc_number] => 05661042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Process for electrically connecting electrical devices using a conductive anisotropic material' [patent_app_type] => 1 [patent_app_number] => 8/520118 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2967 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661042.pdf [firstpage_image] =>[orig_patent_app_number] => 520118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520118
Process for electrically connecting electrical devices using a conductive anisotropic material Aug 27, 1995 Issued
Array ( [id] => 3885756 [patent_doc_number] => 05893723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Manufacturing method for semiconductor unit' [patent_app_type] => 1 [patent_app_number] => 8/519353 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3841 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893723.pdf [firstpage_image] =>[orig_patent_app_number] => 519353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519353
Manufacturing method for semiconductor unit Aug 24, 1995 Issued
Array ( [id] => 3807761 [patent_doc_number] => 05811317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Process for reflow bonding a semiconductor die to a substrate and the product produced by the product' [patent_app_type] => 1 [patent_app_number] => 8/519561 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811317.pdf [firstpage_image] =>[orig_patent_app_number] => 519561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519561
Process for reflow bonding a semiconductor die to a substrate and the product produced by the product Aug 24, 1995 Issued
Array ( [id] => 1485340 [patent_doc_number] => 06365500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Composite bump bonding' [patent_app_type] => B1 [patent_app_number] => 08/518182 [patent_app_country] => US [patent_app_date] => 1995-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365500.pdf [firstpage_image] =>[orig_patent_app_number] => 08518182 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/518182
Composite bump bonding Aug 22, 1995 Issued
08/517670 TAPE AUTOMATED BONDING CIRCUIT WITH INTERIOR SPROCKET HOLES Aug 21, 1995 Abandoned
Array ( [id] => 1454504 [patent_doc_number] => 06425168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Quartz glass jig for heat-treating semiconductor wafers and method for producing same' [patent_app_type] => B1 [patent_app_number] => 08/531023 [patent_app_country] => US [patent_app_date] => 1995-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3405 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425168.pdf [firstpage_image] =>[orig_patent_app_number] => 08531023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/531023
Quartz glass jig for heat-treating semiconductor wafers and method for producing same Aug 19, 1995 Issued
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