Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3734610 [patent_doc_number] => 05698465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Process for manufacturing an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating' [patent_app_type] => 1 [patent_app_number] => 8/474305 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2417 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698465.pdf [firstpage_image] =>[orig_patent_app_number] => 474305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474305
Process for manufacturing an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating Jun 6, 1995 Issued
Array ( [id] => 3993301 [patent_doc_number] => 05985692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Process for flip-chip bonding a semiconductor die having gold bump electrodes' [patent_app_type] => 1 [patent_app_number] => 8/478114 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4247 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985692.pdf [firstpage_image] =>[orig_patent_app_number] => 478114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/478114
Process for flip-chip bonding a semiconductor die having gold bump electrodes Jun 6, 1995 Issued
Array ( [id] => 3725119 [patent_doc_number] => 05700697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method for packaging an integrated circuit using a reconstructed package' [patent_app_type] => 1 [patent_app_number] => 8/471739 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700697.pdf [firstpage_image] =>[orig_patent_app_number] => 471739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/471739
Method for packaging an integrated circuit using a reconstructed package Jun 5, 1995 Issued
Array ( [id] => 4394333 [patent_doc_number] => 06297074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/464577 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 5069 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297074.pdf [firstpage_image] =>[orig_patent_app_number] => 464577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/464577
Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof Jun 4, 1995 Issued
08/463113 METHOD OF ASSEMBLING A SEMICONDUCTOR DEVICE USING A MAGNET Jun 4, 1995 Abandoned
Array ( [id] => 4062476 [patent_doc_number] => 05866436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Process of manufacturing an intergrated circuit having an interferometrically profiled mounting film' [patent_app_type] => 1 [patent_app_number] => 8/454976 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 4568 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866436.pdf [firstpage_image] =>[orig_patent_app_number] => 454976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/454976
Process of manufacturing an intergrated circuit having an interferometrically profiled mounting film May 30, 1995 Issued
08/451561 PROCESS OF TAB BONDING SEMICONDUCTOR DEVICE SIGNAL LEADS TO A CONDUCTIVE LAYER May 25, 1995 Abandoned
Array ( [id] => 3687222 [patent_doc_number] => 05643834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers' [patent_app_type] => 1 [patent_app_number] => 8/450406 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 8675 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643834.pdf [firstpage_image] =>[orig_patent_app_number] => 450406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450406
Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers May 24, 1995 Issued
Array ( [id] => 3734380 [patent_doc_number] => 05698451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method of fabricating contacts for solar cells' [patent_app_type] => 1 [patent_app_number] => 8/448033 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698451.pdf [firstpage_image] =>[orig_patent_app_number] => 448033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448033
Method of fabricating contacts for solar cells May 22, 1995 Issued
08/443042 LOW COST LEAD FRAME DESIGN AND MANUFACTURING PROCESS May 16, 1995 Abandoned
08/442773 JIG USED FOR ASSEMBLING SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES May 16, 1995 Abandoned
Array ( [id] => 3828110 [patent_doc_number] => 05739053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step' [patent_app_type] => 1 [patent_app_number] => 8/440991 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 34 [patent_no_of_words] => 7041 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739053.pdf [firstpage_image] =>[orig_patent_app_number] => 440991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440991
Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step May 14, 1995 Issued
Array ( [id] => 3876723 [patent_doc_number] => 05728601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Process for manufacturing a single in-line package for surface mounting' [patent_app_type] => 1 [patent_app_number] => 8/441595 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4378 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728601.pdf [firstpage_image] =>[orig_patent_app_number] => 441595 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/441595
Process for manufacturing a single in-line package for surface mounting May 14, 1995 Issued
08/440167 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF May 11, 1995 Abandoned
Array ( [id] => 3619841 [patent_doc_number] => 05614441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package' [patent_app_type] => 1 [patent_app_number] => 8/434995 [patent_app_country] => US [patent_app_date] => 1995-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2953 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614441.pdf [firstpage_image] =>[orig_patent_app_number] => 434995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434995
Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package May 3, 1995 Issued
Array ( [id] => 3725387 [patent_doc_number] => 05700715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Process for mounting a semiconductor device to a circuit substrate' [patent_app_type] => 1 [patent_app_number] => 8/434276 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5188 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700715.pdf [firstpage_image] =>[orig_patent_app_number] => 434276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434276
Process for mounting a semiconductor device to a circuit substrate May 2, 1995 Issued
Array ( [id] => 4056722 [patent_doc_number] => 05863810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method for encapsulating an integrated circuit having a window' [patent_app_type] => 1 [patent_app_number] => 8/434909 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3039 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/863/05863810.pdf [firstpage_image] =>[orig_patent_app_number] => 434909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434909
Method for encapsulating an integrated circuit having a window May 2, 1995 Issued
08/431250 HIGH MTF OPTICAL COATING FOR HYBRID UFPA'S Apr 27, 1995 Abandoned
Array ( [id] => 3868957 [patent_doc_number] => 05803932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Resist processing apparatus having an interface section including two stacked substrate waiting tables' [patent_app_type] => 1 [patent_app_number] => 8/427871 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 23413 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/803/05803932.pdf [firstpage_image] =>[orig_patent_app_number] => 427871 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/427871
Resist processing apparatus having an interface section including two stacked substrate waiting tables Apr 25, 1995 Issued
08/427771 RADIANT CHAMBER AND METHOD FOR LID SEAL IN CERAMIC PACKAGING Apr 24, 1995 Abandoned
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