| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05866436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Process of manufacturing an intergrated circuit having an interferometrically profiled mounting film'
[patent_app_type] => 1
[patent_app_number] => 8/454976
[patent_app_country] => US
[patent_app_date] => 1995-05-31
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[firstpage_image] =>[orig_patent_app_number] => 454976
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/454976 | Process of manufacturing an intergrated circuit having an interferometrically profiled mounting film | May 30, 1995 | Issued |
| 08/451561 | PROCESS OF TAB BONDING SEMICONDUCTOR DEVICE SIGNAL LEADS TO A CONDUCTIVE LAYER | May 25, 1995 | Abandoned |
Array
(
[id] => 3687222
[patent_doc_number] => 05643834
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers'
[patent_app_type] => 1
[patent_app_number] => 8/450406
[patent_app_country] => US
[patent_app_date] => 1995-05-25
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[firstpage_image] =>[orig_patent_app_number] => 450406
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/450406 | Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers | May 24, 1995 | Issued |
Array
(
[id] => 3734380
[patent_doc_number] => 05698451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Method of fabricating contacts for solar cells'
[patent_app_type] => 1
[patent_app_number] => 8/448033
[patent_app_country] => US
[patent_app_date] => 1995-05-23
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[firstpage_image] =>[orig_patent_app_number] => 448033
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448033 | Method of fabricating contacts for solar cells | May 22, 1995 | Issued |
| 08/443042 | LOW COST LEAD FRAME DESIGN AND MANUFACTURING PROCESS | May 16, 1995 | Abandoned |
| 08/442773 | JIG USED FOR ASSEMBLING SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES | May 16, 1995 | Abandoned |
Array
(
[id] => 3828110
[patent_doc_number] => 05739053
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step'
[patent_app_type] => 1
[patent_app_number] => 8/440991
[patent_app_country] => US
[patent_app_date] => 1995-05-15
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Array
(
[id] => 3876723
[patent_doc_number] => 05728601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Process for manufacturing a single in-line package for surface mounting'
[patent_app_type] => 1
[patent_app_number] => 8/441595
[patent_app_country] => US
[patent_app_date] => 1995-05-15
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| 08/440167 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | May 11, 1995 | Abandoned |
Array
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[id] => 3619841
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[patent_kind] => NA
[patent_issue_date] => 1997-03-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434995 | Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package | May 3, 1995 | Issued |
Array
(
[id] => 3725387
[patent_doc_number] => 05700715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Process for mounting a semiconductor device to a circuit substrate'
[patent_app_type] => 1
[patent_app_number] => 8/434276
[patent_app_country] => US
[patent_app_date] => 1995-05-03
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[firstpage_image] =>[orig_patent_app_number] => 434276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434276 | Process for mounting a semiconductor device to a circuit substrate | May 2, 1995 | Issued |
Array
(
[id] => 4056722
[patent_doc_number] => 05863810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Method for encapsulating an integrated circuit having a window'
[patent_app_type] => 1
[patent_app_number] => 8/434909
[patent_app_country] => US
[patent_app_date] => 1995-05-03
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[firstpage_image] =>[orig_patent_app_number] => 434909
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434909 | Method for encapsulating an integrated circuit having a window | May 2, 1995 | Issued |
| 08/431250 | HIGH MTF OPTICAL COATING FOR HYBRID UFPA'S | Apr 27, 1995 | Abandoned |
Array
(
[id] => 3868957
[patent_doc_number] => 05803932
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Resist processing apparatus having an interface section including two stacked substrate waiting tables'
[patent_app_type] => 1
[patent_app_number] => 8/427871
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[patent_app_date] => 1995-04-26
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[firstpage_image] =>[orig_patent_app_number] => 427871
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/427871 | Resist processing apparatus having an interface section including two stacked substrate waiting tables | Apr 25, 1995 | Issued |
| 08/427771 | RADIANT CHAMBER AND METHOD FOR LID SEAL IN CERAMIC PACKAGING | Apr 24, 1995 | Abandoned |
Array
(
[id] => 4034840
[patent_doc_number] => 05856235
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[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Process of vacuum annealing a thin film metallization on high purity alumina'
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[firstpage_image] =>[orig_patent_app_number] => 421809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/421809 | Process of vacuum annealing a thin film metallization on high purity alumina | Apr 11, 1995 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Method for forming a metal contact'
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Array
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Array
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Array
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