Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3655915 [patent_doc_number] => 05622873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Process for manufacturing a resin molded image pick-up semiconductor chip having a window' [patent_app_type] => 1 [patent_app_number] => 8/376723 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3001 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622873.pdf [firstpage_image] =>[orig_patent_app_number] => 376723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376723
Process for manufacturing a resin molded image pick-up semiconductor chip having a window Jan 22, 1995 Issued
Array ( [id] => 3687167 [patent_doc_number] => 05643830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Process for manufacturing off-axis power branches for interior bond pad arrangements' [patent_app_type] => 1 [patent_app_number] => 8/377211 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 5728 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643830.pdf [firstpage_image] =>[orig_patent_app_number] => 377211 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/377211
Process for manufacturing off-axis power branches for interior bond pad arrangements Jan 22, 1995 Issued
Array ( [id] => 3519066 [patent_doc_number] => 05529950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method for manufacturing a cubically integrated circuit arrangement' [patent_app_type] => 1 [patent_app_number] => 8/377049 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529950.pdf [firstpage_image] =>[orig_patent_app_number] => 377049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/377049
Method for manufacturing a cubically integrated circuit arrangement Jan 22, 1995 Issued
Array ( [id] => 3522040 [patent_doc_number] => 05489551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of fabricating thin film circuits with high density circuit interconnects by pyrolosis of an adhesive' [patent_app_type] => 1 [patent_app_number] => 8/376209 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2771 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489551.pdf [firstpage_image] =>[orig_patent_app_number] => 376209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376209
Method of fabricating thin film circuits with high density circuit interconnects by pyrolosis of an adhesive Jan 19, 1995 Issued
08/374429 METHOD FOR FABRICATING SOLDER BUMPS BY FORMING SOLDER BALLS Jan 18, 1995 Abandoned
Array ( [id] => 3657701 [patent_doc_number] => 05591649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Process of removing a tape automated bonded semiconductor from bonded leads' [patent_app_type] => 1 [patent_app_number] => 8/375462 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2264 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591649.pdf [firstpage_image] =>[orig_patent_app_number] => 375462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375462
Process of removing a tape automated bonded semiconductor from bonded leads Jan 18, 1995 Issued
08/372363 METAL PLANE SUPPORT FOR MULTI-LAYER LEAD FRAMES AND A PROCESS FOR MANUFACTURING SUCH FRAMES Jan 12, 1995 Abandoned
Array ( [id] => 4348850 [patent_doc_number] => 06190424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Process for fabricating two different types of wafers in a semiconductor wafer production line' [patent_app_type] => 1 [patent_app_number] => 8/371139 [patent_app_country] => US [patent_app_date] => 1995-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5581 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190424.pdf [firstpage_image] =>[orig_patent_app_number] => 371139 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/371139
Process for fabricating two different types of wafers in a semiconductor wafer production line Jan 10, 1995 Issued
08/366357 LINEWIDTH METROLOGY OF INTEGRATED CIRCUIT STRUCTURES Dec 28, 1994 Abandoned
Array ( [id] => 3594535 [patent_doc_number] => 05533243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Notch position aligning apparatus and process for using the apparatus to independently align individual wafers in a wafer cassette' [patent_app_type] => 1 [patent_app_number] => 8/365429 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4270 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/533/05533243.pdf [firstpage_image] =>[orig_patent_app_number] => 365429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/365429
Notch position aligning apparatus and process for using the apparatus to independently align individual wafers in a wafer cassette Dec 27, 1994 Issued
Array ( [id] => 3824381 [patent_doc_number] => 05731224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Method for manufacturing ohmic contacts for compound semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/365243 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2012 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731224.pdf [firstpage_image] =>[orig_patent_app_number] => 365243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/365243
Method for manufacturing ohmic contacts for compound semiconductors Dec 27, 1994 Issued
08/364087 INTEGRATED CIRCUIT PACKAGE ENCAPSULATED BY FIBER LADEN MOLDING MATERIAL AND ITS METHOD OF MANUFACTURING Dec 26, 1994 Abandoned
Array ( [id] => 3597958 [patent_doc_number] => 05559051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider' [patent_app_type] => 1 [patent_app_number] => 8/363465 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 4332 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559051.pdf [firstpage_image] =>[orig_patent_app_number] => 363465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/363465
Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider Dec 22, 1994 Issued
Array ( [id] => 3423575 [patent_doc_number] => 05459081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Process for transferring a device to a substrate by viewing a registration pattern' [patent_app_type] => 1 [patent_app_number] => 8/357935 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3607 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459081.pdf [firstpage_image] =>[orig_patent_app_number] => 357935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357935
Process for transferring a device to a substrate by viewing a registration pattern Dec 15, 1994 Issued
Array ( [id] => 3495956 [patent_doc_number] => 05532187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Process for sealing apertures in glass-silicon-glass micromechanical acceleration sensors' [patent_app_type] => 1 [patent_app_number] => 8/357801 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2467 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532187.pdf [firstpage_image] =>[orig_patent_app_number] => 357801 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357801
Process for sealing apertures in glass-silicon-glass micromechanical acceleration sensors Dec 15, 1994 Issued
Array ( [id] => 3924220 [patent_doc_number] => 05972051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and apparatus for removing particles from semiconductor wafer edges using a particle withdrawing means' [patent_app_type] => 1 [patent_app_number] => 8/357086 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5164 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972051.pdf [firstpage_image] =>[orig_patent_app_number] => 357086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357086
Method and apparatus for removing particles from semiconductor wafer edges using a particle withdrawing means Dec 14, 1994 Issued
Array ( [id] => 3687157 [patent_doc_number] => 05643829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method for the fabrication of multilayer electroluminescence device' [patent_app_type] => 1 [patent_app_number] => 8/355777 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3182 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643829.pdf [firstpage_image] =>[orig_patent_app_number] => 355777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355777
Method for the fabrication of multilayer electroluminescence device Dec 13, 1994 Issued
08/354261 INTEGRATED CIRCUIT WITH LEAD FRAME PACKAGE HAVING INTERNAL POWER AND GROUND BUSSES Dec 11, 1994 Abandoned
08/352301 METHOD AND APPARATUS FOR IN-SITU TESTING OF INTEGRATED CIRCUIT CHIPS Dec 7, 1994 Abandoned
08/351761 PROCESS FOR FABRICATING AN ELECTRONIC CIRCUIT PACKAGE Dec 7, 1994 Abandoned
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