Search

David E. Graybill

Examiner (ID: 7668, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2814, 2894, 2822, 3727, 1107, 2827, 1763, 2812
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4097621 [patent_doc_number] => 06048754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method of manufacturing a semiconductor device with an airtight space formed internally within a hollow package' [patent_app_type] => 1 [patent_app_number] => 8/260977 [patent_app_country] => US [patent_app_date] => 1994-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4357 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048754.pdf [firstpage_image] =>[orig_patent_app_number] => 260977 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/260977
Method of manufacturing a semiconductor device with an airtight space formed internally within a hollow package Jun 14, 1994 Issued
08/259439 TECHNIQUES FOR ISOLATING SUPERCONDUCTING SUBSTRATES FROM HEAT GENERATED BY SEMICONDUCTOR DEVICES Jun 13, 1994 Abandoned
Array ( [id] => 3982621 [patent_doc_number] => 05861323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Process for manufacturing metal ball electrodes for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/270661 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4661 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861323.pdf [firstpage_image] =>[orig_patent_app_number] => 270661 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270661
Process for manufacturing metal ball electrodes for a semiconductor device Jun 5, 1994 Issued
Array ( [id] => 3442134 [patent_doc_number] => 05466635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating' [patent_app_type] => 1 [patent_app_number] => 8/252691 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2416 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/466/05466635.pdf [firstpage_image] =>[orig_patent_app_number] => 252691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252691
Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating Jun 1, 1994 Issued
Array ( [id] => 3814965 [patent_doc_number] => 05770468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere' [patent_app_type] => 1 [patent_app_number] => 8/245657 [patent_app_country] => US [patent_app_date] => 1994-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 51 [patent_no_of_words] => 5994 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770468.pdf [firstpage_image] =>[orig_patent_app_number] => 245657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/245657
Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere May 17, 1994 Issued
08/239375 COMPOSITE BUMP BONDING May 5, 1994 Abandoned
Array ( [id] => 3426699 [patent_doc_number] => 05403754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Lithography method for direct alignment of integrated circuits multiple layers' [patent_app_type] => 1 [patent_app_number] => 8/238194 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2245 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403754.pdf [firstpage_image] =>[orig_patent_app_number] => 238194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/238194
Lithography method for direct alignment of integrated circuits multiple layers May 3, 1994 Issued
08/237173 PROCESS OF FABRICATING SEMICONDUCTOR UNIT EMPLOYING BUMPS TO BOND TWO COMPONENTS May 2, 1994 Abandoned
08/235849 ENCAPSULATE RESIN LOC PACKAGE AND METHOD OF FABRICATION Apr 28, 1994 Abandoned
08/233941 OPTICAL SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME Apr 27, 1994 Abandoned
Array ( [id] => 4394361 [patent_doc_number] => 06297076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for preparing a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 8/234073 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 7665 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297076.pdf [firstpage_image] =>[orig_patent_app_number] => 234073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234073
Process for preparing a semiconductor wafer Apr 27, 1994 Issued
Array ( [id] => 3606024 [patent_doc_number] => 05565008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Process of raising a semiconductor device out of a pallet using a positioning rod' [patent_app_type] => 1 [patent_app_number] => 8/234595 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 3599 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565008.pdf [firstpage_image] =>[orig_patent_app_number] => 234595 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234595
Process of raising a semiconductor device out of a pallet using a positioning rod Apr 27, 1994 Issued
Array ( [id] => 3832071 [patent_doc_number] => 05712192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Process for connecting an electrical device to a circuit substrate' [patent_app_type] => 1 [patent_app_number] => 8/233193 [patent_app_country] => US [patent_app_date] => 1994-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712192.pdf [firstpage_image] =>[orig_patent_app_number] => 233193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/233193
Process for connecting an electrical device to a circuit substrate Apr 25, 1994 Issued
Array ( [id] => 3460051 [patent_doc_number] => 05391514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Low temperature ternary C4 flip chip bonding method' [patent_app_type] => 1 [patent_app_number] => 8/229883 [patent_app_country] => US [patent_app_date] => 1994-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391514.pdf [firstpage_image] =>[orig_patent_app_number] => 229883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229883
Low temperature ternary C4 flip chip bonding method Apr 18, 1994 Issued
Array ( [id] => 3717185 [patent_doc_number] => 05681356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Method and apparatus for producing a plastic molded chip card having reduced wall thickness' [patent_app_type] => 1 [patent_app_number] => 8/146087 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5726 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681356.pdf [firstpage_image] =>[orig_patent_app_number] => 146087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/146087
Method and apparatus for producing a plastic molded chip card having reduced wall thickness Apr 4, 1994 Issued
Array ( [id] => 3470033 [patent_doc_number] => 05431700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Vertical multi-process bake/chill apparatus' [patent_app_type] => 1 [patent_app_number] => 8/220235 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2829 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/431/05431700.pdf [firstpage_image] =>[orig_patent_app_number] => 220235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220235
Vertical multi-process bake/chill apparatus Mar 29, 1994 Issued
Array ( [id] => 3553101 [patent_doc_number] => 05518957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method for making a thin profile semiconductor package' [patent_app_type] => 1 [patent_app_number] => 8/218939 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1317 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518957.pdf [firstpage_image] =>[orig_patent_app_number] => 218939 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218939
Method for making a thin profile semiconductor package Mar 27, 1994 Issued
Array ( [id] => 3855755 [patent_doc_number] => 05705424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Process of fabricating active matrix pixel electrodes' [patent_app_type] => 1 [patent_app_number] => 8/215555 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 47 [patent_no_of_words] => 5344 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705424.pdf [firstpage_image] =>[orig_patent_app_number] => 215555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215555
Process of fabricating active matrix pixel electrodes Mar 20, 1994 Issued
08/213149 3D STACK OF IC CHIPS HAVING LEADS REACHED BY VIAS THROUGH PASSIVATION COVERING ACCESS PLANE Mar 14, 1994 Abandoned
08/207493 THERMAL COOLING OF PACKAGED SEMICONDUCTOR DEVICES Mar 6, 1994 Abandoned
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