Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3470033 [patent_doc_number] => 05431700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Vertical multi-process bake/chill apparatus' [patent_app_type] => 1 [patent_app_number] => 8/220235 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2829 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/431/05431700.pdf [firstpage_image] =>[orig_patent_app_number] => 220235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220235
Vertical multi-process bake/chill apparatus Mar 29, 1994 Issued
Array ( [id] => 3553101 [patent_doc_number] => 05518957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method for making a thin profile semiconductor package' [patent_app_type] => 1 [patent_app_number] => 8/218939 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1317 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518957.pdf [firstpage_image] =>[orig_patent_app_number] => 218939 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218939
Method for making a thin profile semiconductor package Mar 27, 1994 Issued
Array ( [id] => 3855755 [patent_doc_number] => 05705424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Process of fabricating active matrix pixel electrodes' [patent_app_type] => 1 [patent_app_number] => 8/215555 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 47 [patent_no_of_words] => 5344 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705424.pdf [firstpage_image] =>[orig_patent_app_number] => 215555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215555
Process of fabricating active matrix pixel electrodes Mar 20, 1994 Issued
08/213149 3D STACK OF IC CHIPS HAVING LEADS REACHED BY VIAS THROUGH PASSIVATION COVERING ACCESS PLANE Mar 14, 1994 Abandoned
08/207493 THERMAL COOLING OF PACKAGED SEMICONDUCTOR DEVICES Mar 6, 1994 Abandoned
Array ( [id] => 3417561 [patent_doc_number] => 05434105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Process for attaching a lead frame to a heat sink using a glob-top encapsulation' [patent_app_type] => 1 [patent_app_number] => 8/206011 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2078 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434105.pdf [firstpage_image] =>[orig_patent_app_number] => 206011 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/206011
Process for attaching a lead frame to a heat sink using a glob-top encapsulation Mar 3, 1994 Issued
Array ( [id] => 3107381 [patent_doc_number] => 05407865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Method of manufacturing a flexible metallized polymer film cover for environmental protection of electronic assemblies' [patent_app_type] => 1 [patent_app_number] => 8/206309 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1867 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407865.pdf [firstpage_image] =>[orig_patent_app_number] => 206309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/206309
Method of manufacturing a flexible metallized polymer film cover for environmental protection of electronic assemblies Mar 3, 1994 Issued
Array ( [id] => 3489008 [patent_doc_number] => 05470795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Method of connecting terminals of a plastic-encapsulated power transistor to a printed-circuit board' [patent_app_type] => 1 [patent_app_number] => 8/201657 [patent_app_country] => US [patent_app_date] => 1994-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3801 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/470/05470795.pdf [firstpage_image] =>[orig_patent_app_number] => 201657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/201657
Method of connecting terminals of a plastic-encapsulated power transistor to a printed-circuit board Feb 24, 1994 Issued
Array ( [id] => 3731107 [patent_doc_number] => 05665639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal' [patent_app_type] => 1 [patent_app_number] => 8/200673 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6073 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665639.pdf [firstpage_image] =>[orig_patent_app_number] => 200673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/200673
Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal Feb 22, 1994 Issued
Array ( [id] => 3480542 [patent_doc_number] => 05457072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Process for dicing a semiconductor wafer having a plated heat sink using a temporary substrate' [patent_app_type] => 1 [patent_app_number] => 8/196757 [patent_app_country] => US [patent_app_date] => 1994-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 49 [patent_no_of_words] => 3519 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457072.pdf [firstpage_image] =>[orig_patent_app_number] => 196757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/196757
Process for dicing a semiconductor wafer having a plated heat sink using a temporary substrate Feb 14, 1994 Issued
Array ( [id] => 3102266 [patent_doc_number] => 05447888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Process of ejecting an encapsulated semiconductor device from a mold by directly contacting exterior leads with ejector pins' [patent_app_type] => 1 [patent_app_number] => 8/194343 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4111 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447888.pdf [firstpage_image] =>[orig_patent_app_number] => 194343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/194343
Process of ejecting an encapsulated semiconductor device from a mold by directly contacting exterior leads with ejector pins Feb 7, 1994 Issued
Array ( [id] => 3587449 [patent_doc_number] => 05550087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Process for bonding a semiconductor die to a variable die size inner lead layout' [patent_app_type] => 1 [patent_app_number] => 8/176700 [patent_app_country] => US [patent_app_date] => 1994-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4590 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550087.pdf [firstpage_image] =>[orig_patent_app_number] => 176700 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/176700
Process for bonding a semiconductor die to a variable die size inner lead layout Jan 2, 1994 Issued
08/170613 BALL-GRID-ARRAY INTEGRATED CIRCUIT PACKAGE WITH THERMAL CONDUCTIVITY Dec 19, 1993 Abandoned
08/168079 METHOD FOR PROVIDING KNOWN GOOD BARE SEMICONDUCTOR DIE Dec 14, 1993 Abandoned
Array ( [id] => 3539547 [patent_doc_number] => 05480834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent' [patent_app_type] => 1 [patent_app_number] => 8/166747 [patent_app_country] => US [patent_app_date] => 1993-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1333 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/480/05480834.pdf [firstpage_image] =>[orig_patent_app_number] => 166747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166747
Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent Dec 12, 1993 Issued
Array ( [id] => 3476368 [patent_doc_number] => 05432127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads' [patent_app_type] => 1 [patent_app_number] => 8/161993 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3937 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432127.pdf [firstpage_image] =>[orig_patent_app_number] => 161993 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161993
Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads Dec 1, 1993 Issued
08/160064 OPTO-ELECTRONIC COMPONENTS Nov 29, 1993 Abandoned
08/155880 PACKAGE FOR MATING WITH A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURE Nov 22, 1993 Abandoned
Array ( [id] => 3427081 [patent_doc_number] => 05403776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Process of using a jig to align and mount terminal conductors to a semiconductor plastic package' [patent_app_type] => 1 [patent_app_number] => 8/152239 [patent_app_country] => US [patent_app_date] => 1993-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3199 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403776.pdf [firstpage_image] =>[orig_patent_app_number] => 152239 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/152239
Process of using a jig to align and mount terminal conductors to a semiconductor plastic package Nov 15, 1993 Issued
Array ( [id] => 4147607 [patent_doc_number] => 06156078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Testing and finishing apparatus for integrated circuit package units' [patent_app_type] => 1 [patent_app_number] => 8/152192 [patent_app_country] => US [patent_app_date] => 1993-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 3237 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 705 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156078.pdf [firstpage_image] =>[orig_patent_app_number] => 152192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/152192
Testing and finishing apparatus for integrated circuit package units Nov 11, 1993 Issued
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