| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 3964526
[patent_doc_number] => 05885850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Method for the 3D interconnection of packages of electronic components, and device obtained by this method'
[patent_app_type] => 1
[patent_app_number] => 8/146099
[patent_app_country] => US
[patent_app_date] => 1993-11-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/146099 | Method for the 3D interconnection of packages of electronic components, and device obtained by this method | Nov 9, 1993 | Issued |
| 08/146825 | METHOD FOR FORMING A METAL CONTACT | Oct 31, 1993 | Abandoned |
| 08/146824 | METHOD FOR FORMING A METAL CONTACT | Oct 31, 1993 | Abandoned |
| 08/140473 | METHOD OF FABRICATING SEMICONDUCTOR APPARATUS | Oct 24, 1993 | Abandoned |
| 08/137675 | RAISED PORTIONS OF BONDPAD ATTACHMENTS HAVING SELF-LIMITING PROPERTY | Oct 13, 1993 | Abandoned |
Array
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[id] => 3109620
[patent_doc_number] => 05413970
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Process for manufacturing a semiconductor package having two rows of interdigitated leads'
[patent_app_type] => 1
[patent_app_number] => 8/134149
[patent_app_country] => US
[patent_app_date] => 1993-10-08
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[pdf_file] => patents/05/413/05413970.pdf
[firstpage_image] =>[orig_patent_app_number] => 134149
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/134149 | Process for manufacturing a semiconductor package having two rows of interdigitated leads | Oct 7, 1993 | Issued |
Array
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[id] => 3410128
[patent_doc_number] => 05438020
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Process for flip-chip bonding a semiconductor chip using wire leads'
[patent_app_type] => 1
[patent_app_number] => 8/121881
[patent_app_country] => US
[patent_app_date] => 1993-09-17
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[firstpage_image] =>[orig_patent_app_number] => 121881
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/121881 | Process for flip-chip bonding a semiconductor chip using wire leads | Sep 16, 1993 | Issued |
Array
(
[id] => 3580286
[patent_doc_number] => 05539550
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Liquid crystal display having adhered circuit tiles'
[patent_app_type] => 1
[patent_app_number] => 8/119292
[patent_app_country] => US
[patent_app_date] => 1993-09-09
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 119292
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/119292 | Liquid crystal display having adhered circuit tiles | Sep 8, 1993 | Issued |
| 08/114705 | LOW COST LEAD FRAME DESIGN AND MANUFACTURING PROCESS | Aug 30, 1993 | Abandoned |
Array
(
[id] => 2989011
[patent_doc_number] => 05346836
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects'
[patent_app_type] => 1
[patent_app_number] => 8/108147
[patent_app_country] => US
[patent_app_date] => 1993-08-17
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[firstpage_image] =>[orig_patent_app_number] => 108147
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/108147 | Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects | Aug 16, 1993 | Issued |
Array
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[id] => 3524606
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[patent_issue_date] => 1996-04-02
[patent_title] => 'Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate'
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[firstpage_image] =>[orig_patent_app_number] => 105547
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/105547 | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate | Aug 11, 1993 | Issued |
Array
(
[id] => 3552320
[patent_doc_number] => 05492866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Process for correcting warped surface of plastic encapsulated semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/100323
[patent_app_country] => US
[patent_app_date] => 1993-08-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/492/05492866.pdf
[firstpage_image] =>[orig_patent_app_number] => 100323
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/100323 | Process for correcting warped surface of plastic encapsulated semiconductor device | Aug 1, 1993 | Issued |
| 08/096539 | TAB SEMICONDUCTOR DEVICE WITH SELF-ALIGNING CAVITY AND INTRINSIC STANDOFF AND METHOD FOR MAKING THE SAME | Jul 25, 1993 | Pending |
Array
(
[id] => 3107361
[patent_doc_number] => 05407864
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip'
[patent_app_type] => 1
[patent_app_number] => 8/095375
[patent_app_country] => US
[patent_app_date] => 1993-07-23
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[pdf_file] => patents/05/407/05407864.pdf
[firstpage_image] =>[orig_patent_app_number] => 095375
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/095375 | Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip | Jul 22, 1993 | Issued |
Array
(
[id] => 3006717
[patent_doc_number] => 05354711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Process for etching and depositing integrated circuit interconnections and contacts'
[patent_app_type] => 1
[patent_app_number] => 8/089408
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089408 | Process for etching and depositing integrated circuit interconnections and contacts | Jul 7, 1993 | Issued |
Array
(
[id] => 3439315
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Process for manufacturing semiconductor wafers having deformation ground in a defined way'
[patent_app_type] => 1
[patent_app_number] => 8/088171
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/088171 | Process for manufacturing semiconductor wafers having deformation ground in a defined way | Jul 6, 1993 | Issued |
Array
(
[id] => 3051795
[patent_doc_number] => 05350428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Electrostatic apparatus and method for removing particles from semiconductor wafers'
[patent_app_type] => 1
[patent_app_number] => 8/080165
[patent_app_country] => US
[patent_app_date] => 1993-06-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/080165 | Electrostatic apparatus and method for removing particles from semiconductor wafers | Jun 16, 1993 | Issued |
| 08/080167 | METHOD AND APPARATUS FOR REMOVING PARTICLES FROM SEMICONDUCTOR WAFERS USING A PARTICLE WITHDRAWING MEANS | Jun 16, 1993 | Pending |
| 90/003099 | METHOD OF ENCAPSULATING A SEMICONDUCTOR ELEMENT USING A RESIN MOLD HAVING UPPER AND LOWER MOLD HALF RESIN INFLOW OPENINGS | Jun 15, 1993 | Issued |
Array
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[patent_issue_date] => 1994-09-27
[patent_title] => 'Wafer retaining platen having peripheral clamp and wafer lifting means'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/076509 | Wafer retaining platen having peripheral clamp and wafer lifting means | Jun 13, 1993 | Issued |