| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3014931
[patent_doc_number] => 05340767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-23
[patent_title] => 'Method of forming and selectively coupling a plurality of modules on an integrated circuit chip'
[patent_app_type] => 1
[patent_app_number] => 8/042848
[patent_app_country] => US
[patent_app_date] => 1993-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/340/05340767.pdf
[firstpage_image] =>[orig_patent_app_number] => 042848
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/042848 | Method of forming and selectively coupling a plurality of modules on an integrated circuit chip | Apr 4, 1993 | Issued |
Array
(
[id] => 3456070
[patent_doc_number] => 05401675
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Method of depositing conductors in high aspect ratio apertures using a collimator'
[patent_app_type] => 1
[patent_app_number] => 8/036224
[patent_app_country] => US
[patent_app_date] => 1993-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3835
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[pdf_file] => patents/05/401/05401675.pdf
[firstpage_image] =>[orig_patent_app_number] => 036224
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/036224 | Method of depositing conductors in high aspect ratio apertures using a collimator | Mar 23, 1993 | Issued |
Array
(
[id] => 2999688
[patent_doc_number] => 05371029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Process for making a leadless chip resistor capacitor carrier using thick and thin film printing'
[patent_app_type] => 1
[patent_app_number] => 8/037487
[patent_app_country] => US
[patent_app_date] => 1993-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3904
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
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[pdf_file] => patents/05/371/05371029.pdf
[firstpage_image] =>[orig_patent_app_number] => 037487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/037487 | Process for making a leadless chip resistor capacitor carrier using thick and thin film printing | Mar 23, 1993 | Issued |
| 08/028002 | MOLDING PROCESS FOR ENCAPSULATING SEMICONDUCTOR DEVICES | Mar 7, 1993 | Pending |
| 08/024549 | METHOD AND APPARATUS FOR IN-SITU TESTING OF INTEGRATED CIRCUIT CHIPS | Feb 28, 1993 | Abandoned |
| 08/014481 | EMBEDDED SUBSTRATES FOR INTEGRATED CIRCUIT MODULES | Feb 7, 1993 | Abandoned |
| 08/014769 | METHOD AND APPARATUS FOR MANUFACTURING THERMOPLASTIC RESIN MOLDED SEMICONDUCTOR DEVICE | Feb 7, 1993 | Abandoned |
Array
(
[id] => 3006435
[patent_doc_number] => 05330919
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane'
[patent_app_type] => 1
[patent_app_number] => 8/014591
[patent_app_country] => US
[patent_app_date] => 1993-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4212
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/330/05330919.pdf
[firstpage_image] =>[orig_patent_app_number] => 014591
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/014591 | Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane | Feb 7, 1993 | Issued |
Array
(
[id] => 3095303
[patent_doc_number] => 05318926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-07
[patent_title] => 'Method for packaging an integrated circuit using a reconstructed plastic package'
[patent_app_type] => 1
[patent_app_number] => 8/011957
[patent_app_country] => US
[patent_app_date] => 1993-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4241
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/318/05318926.pdf
[firstpage_image] =>[orig_patent_app_number] => 011957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/011957 | Method for packaging an integrated circuit using a reconstructed plastic package | Jan 31, 1993 | Issued |
Array
(
[id] => 3427210
[patent_doc_number] => 05403784
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template'
[patent_app_type] => 1
[patent_app_number] => 8/008044
[patent_app_country] => US
[patent_app_date] => 1993-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/403/05403784.pdf
[firstpage_image] =>[orig_patent_app_number] => 008044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/008044 | Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template | Jan 28, 1993 | Issued |
| 08/010457 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE | Jan 26, 1993 | Abandoned |
| 08/007877 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING HIGH MOUNTING DENSITY AND ITS MOUNTING METHOD | Jan 21, 1993 | Abandoned |
Array
(
[id] => 3487123
[patent_doc_number] => 05426072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-20
[patent_title] => 'Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate'
[patent_app_type] => 1
[patent_app_number] => 8/006601
[patent_app_country] => US
[patent_app_date] => 1993-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4085
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/426/05426072.pdf
[firstpage_image] =>[orig_patent_app_number] => 006601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/006601 | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate | Jan 20, 1993 | Issued |
Array
(
[id] => 7636657
[patent_doc_number] => 06379998
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 08/007061
[patent_app_country] => US
[patent_app_date] => 1993-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[patent_no_of_words] => 13707
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/379/06379998.pdf
[firstpage_image] =>[orig_patent_app_number] => 08007061
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/007061 | Semiconductor device and method for fabricating the same | Jan 20, 1993 | Issued |
| 08/006120 | PROCESS OF MANUFACTURING A MICROELECTRONIC DEVICE USING A REMOVABLE SUPPORT SUBSTRATE AND ETCH-STOP | Jan 18, 1993 | Abandoned |
Array
(
[id] => 3064579
[patent_doc_number] => 05352629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules'
[patent_app_type] => 1
[patent_app_number] => 8/006297
[patent_app_country] => US
[patent_app_date] => 1993-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2555
[patent_no_of_claims] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/352/05352629.pdf
[firstpage_image] =>[orig_patent_app_number] => 006297
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/006297 | Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules | Jan 18, 1993 | Issued |
Array
(
[id] => 3061779
[patent_doc_number] => 05310701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-10
[patent_title] => 'Method for fixing semiconductor bodies on a substrate using wires'
[patent_app_type] => 1
[patent_app_number] => 8/003539
[patent_app_country] => US
[patent_app_date] => 1993-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 1267
[patent_no_of_claims] => 6
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/310/05310701.pdf
[firstpage_image] =>[orig_patent_app_number] => 003539
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/003539 | Method for fixing semiconductor bodies on a substrate using wires | Jan 12, 1993 | Issued |
Array
(
[id] => 3611555
[patent_doc_number] => 05565378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Process of passivating a semiconductor device bonding pad by immersion in O.sub.2 or O.sub.3 solution'
[patent_app_type] => 1
[patent_app_number] => 7/997833
[patent_app_country] => US
[patent_app_date] => 1992-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] => patents/05/565/05565378.pdf
[firstpage_image] =>[orig_patent_app_number] => 997833
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/997833 | Process of passivating a semiconductor device bonding pad by immersion in O.sub.2 or O.sub.3 solution | Dec 28, 1992 | Issued |
Array
(
[id] => 3113353
[patent_doc_number] => 05409866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe'
[patent_app_type] => 1
[patent_app_number] => 7/996589
[patent_app_country] => US
[patent_app_date] => 1992-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[pdf_file] => patents/05/409/05409866.pdf
[firstpage_image] =>[orig_patent_app_number] => 996589
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/996589 | Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe | Dec 23, 1992 | Issued |
Array
(
[id] => 3083549
[patent_doc_number] => 05279991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Method for fabricating stacks of IC chips by segmenting a larger stack'
[patent_app_type] => 1
[patent_app_number] => 7/996794
[patent_app_country] => US
[patent_app_date] => 1992-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 6824
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/279/05279991.pdf
[firstpage_image] =>[orig_patent_app_number] => 996794
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/996794 | Method for fabricating stacks of IC chips by segmenting a larger stack | Dec 23, 1992 | Issued |