Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2982917 [patent_doc_number] => 05346513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for producing semiconductor device using a vacuum sealing mechanism having inner and outer bellows' [patent_app_type] => 1 [patent_app_number] => 8/065756 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346513.pdf [firstpage_image] =>[orig_patent_app_number] => 065756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/065756
Method for producing semiconductor device using a vacuum sealing mechanism having inner and outer bellows May 23, 1993 Issued
08/064291 METHOD FOR MAKING A BALANCED CAPACITANCE LEAD FRAME FOR INTERGRATED CIRCUITS HAVING A POWER BUS AND DUMMY LEADS May 17, 1993 Pending
Array ( [id] => 3045754 [patent_doc_number] => 05304513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame' [patent_app_type] => 1 [patent_app_number] => 8/060704 [patent_app_country] => US [patent_app_date] => 1993-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2190 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304513.pdf [firstpage_image] =>[orig_patent_app_number] => 060704 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/060704
Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame May 12, 1993 Issued
Array ( [id] => 3456237 [patent_doc_number] => 05401687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures' [patent_app_type] => 1 [patent_app_number] => 8/046299 [patent_app_country] => US [patent_app_date] => 1993-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4689 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/401/05401687.pdf [firstpage_image] =>[orig_patent_app_number] => 046299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/046299
Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures Apr 14, 1993 Issued
08/046189 SILICONE OVERMOLD OF A FLIP-CHIP DEVICE Apr 11, 1993 Pending
Array ( [id] => 3014931 [patent_doc_number] => 05340767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method of forming and selectively coupling a plurality of modules on an integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 8/042848 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 7075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/340/05340767.pdf [firstpage_image] =>[orig_patent_app_number] => 042848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/042848
Method of forming and selectively coupling a plurality of modules on an integrated circuit chip Apr 4, 1993 Issued
Array ( [id] => 2999688 [patent_doc_number] => 05371029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Process for making a leadless chip resistor capacitor carrier using thick and thin film printing' [patent_app_type] => 1 [patent_app_number] => 8/037487 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3904 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371029.pdf [firstpage_image] =>[orig_patent_app_number] => 037487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/037487
Process for making a leadless chip resistor capacitor carrier using thick and thin film printing Mar 23, 1993 Issued
Array ( [id] => 3456070 [patent_doc_number] => 05401675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Method of depositing conductors in high aspect ratio apertures using a collimator' [patent_app_type] => 1 [patent_app_number] => 8/036224 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3835 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/401/05401675.pdf [firstpage_image] =>[orig_patent_app_number] => 036224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/036224
Method of depositing conductors in high aspect ratio apertures using a collimator Mar 23, 1993 Issued
08/028002 MOLDING PROCESS FOR ENCAPSULATING SEMICONDUCTOR DEVICES Mar 7, 1993 Pending
08/024549 METHOD AND APPARATUS FOR IN-SITU TESTING OF INTEGRATED CIRCUIT CHIPS Feb 28, 1993 Abandoned
08/014481 EMBEDDED SUBSTRATES FOR INTEGRATED CIRCUIT MODULES Feb 7, 1993 Abandoned
Array ( [id] => 3006435 [patent_doc_number] => 05330919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane' [patent_app_type] => 1 [patent_app_number] => 8/014591 [patent_app_country] => US [patent_app_date] => 1993-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4212 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/330/05330919.pdf [firstpage_image] =>[orig_patent_app_number] => 014591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014591
Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane Feb 7, 1993 Issued
08/014769 METHOD AND APPARATUS FOR MANUFACTURING THERMOPLASTIC RESIN MOLDED SEMICONDUCTOR DEVICE Feb 7, 1993 Abandoned
Array ( [id] => 3095303 [patent_doc_number] => 05318926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Method for packaging an integrated circuit using a reconstructed plastic package' [patent_app_type] => 1 [patent_app_number] => 8/011957 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4241 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/318/05318926.pdf [firstpage_image] =>[orig_patent_app_number] => 011957 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/011957
Method for packaging an integrated circuit using a reconstructed plastic package Jan 31, 1993 Issued
Array ( [id] => 3427210 [patent_doc_number] => 05403784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template' [patent_app_type] => 1 [patent_app_number] => 8/008044 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 41 [patent_no_of_words] => 5496 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403784.pdf [firstpage_image] =>[orig_patent_app_number] => 008044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/008044
Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template Jan 28, 1993 Issued
08/010457 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE Jan 26, 1993 Abandoned
08/007877 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING HIGH MOUNTING DENSITY AND ITS MOUNTING METHOD Jan 21, 1993 Abandoned
Array ( [id] => 7636657 [patent_doc_number] => 06379998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 08/007061 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 73 [patent_no_of_words] => 13707 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/379/06379998.pdf [firstpage_image] =>[orig_patent_app_number] => 08007061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/007061
Semiconductor device and method for fabricating the same Jan 20, 1993 Issued
Array ( [id] => 3487123 [patent_doc_number] => 05426072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate' [patent_app_type] => 1 [patent_app_number] => 8/006601 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4085 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426072.pdf [firstpage_image] =>[orig_patent_app_number] => 006601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/006601
Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate Jan 20, 1993 Issued
08/006120 PROCESS OF MANUFACTURING A MICROELECTRONIC DEVICE USING A REMOVABLE SUPPORT SUBSTRATE AND ETCH-STOP Jan 18, 1993 Abandoned
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