David E. Graybill

Array ( [id] => 3024125 [patent_doc_number] => 05316787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Method for manufacturing electrically isolated polyimide coated vias in a flexible substrate' [patent_app_type] => 1 [patent_app_number] => 7/978309 [patent_app_country] => US [patent_app_date] => 1992-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/316/05316787.pdf [firstpage_image] =>[orig_patent_app_number] => 978309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2893686 [patent_doc_number] => 05272113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'Method for minimizing stress between semiconductor chips having a coefficient of thermal expansion different from that of a mounting substrate' [patent_app_type] => 1 [patent_app_number] => 7/974567 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3138 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272113.pdf [firstpage_image] =>[orig_patent_app_number] => 974567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3034036 [patent_doc_number] => 05300459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Method for reducing thermal stress in an encapsulated integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 7/971329 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300459.pdf [firstpage_image] =>[orig_patent_app_number] => 971329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2974511 [patent_doc_number] => 05256562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method for manufacturing a semiconductor device using a circuit transfer film' [patent_app_type] => 1 [patent_app_number] => 7/970675 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 5003 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/256/05256562.pdf [firstpage_image] =>[orig_patent_app_number] => 970675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2953907 [patent_doc_number] => 05264002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Method for conveying semiconductor lead frame strip with an apparatus having vertically movable guide rails' [patent_app_type] => 1 [patent_app_number] => 7/969384 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2567 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/264/05264002.pdf [firstpage_image] =>[orig_patent_app_number] => 969384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3442057 [patent_doc_number] => 05387265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Semiconductor wafer reaction furnace with wafer transfer means' [patent_app_type] => 1 [patent_app_number] => 7/966721 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387265.pdf [firstpage_image] =>[orig_patent_app_number] => 966721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365422 [patent_doc_number] => 06274391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'HDI land grid array packaged device having electrical and optical interconnects' [patent_app_type] => 1 [patent_app_number] => 7/966645 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 7336 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274391.pdf [firstpage_image] =>[orig_patent_app_number] => 966645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3446374 [patent_doc_number] => 05387547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Process for adjusting the impedance of a microwave conductor using an air bridge' [patent_app_type] => 1 [patent_app_number] => 7/965319 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3000 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387547.pdf [firstpage_image] =>[orig_patent_app_number] => 965319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2894306 [patent_doc_number] => 05244840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method for manufacturing an encapsulated IC card having a molded frame and a circuit board' [patent_app_type] => 1 [patent_app_number] => 7/963699 [patent_app_country] => US [patent_app_date] => 1992-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 4628 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244840.pdf [firstpage_image] =>[orig_patent_app_number] => 963699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2989421 [patent_doc_number] => 05346857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for forming a flip-chip bond from a gold-tin eutectic' [patent_app_type] => 1 [patent_app_number] => 7/952005 [patent_app_country] => US [patent_app_date] => 1992-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346857.pdf [firstpage_image] =>[orig_patent_app_number] => 952005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2916619 [patent_doc_number] => 05206186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method for forming semiconductor electrical contacts using metal foil and thermocompression bonding' [patent_app_type] => 1 [patent_app_number] => 7/950553 [patent_app_country] => US [patent_app_date] => 1992-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3063 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206186.pdf [firstpage_image] =>[orig_patent_app_number] => 950553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3052287 [patent_doc_number] => 05344795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Method for encapsulating an integrated circuit using a removable heatsink support block' [patent_app_type] => 1 [patent_app_number] => 7/949189 [patent_app_country] => US [patent_app_date] => 1992-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3453 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/344/05344795.pdf [firstpage_image] =>[orig_patent_app_number] => 949189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3086233 [patent_doc_number] => 05278098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Method for self-aligned polysilicon contact formation' [patent_app_type] => 1 [patent_app_number] => 7/939951 [patent_app_country] => US [patent_app_date] => 1992-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3975 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278098.pdf [firstpage_image] =>[orig_patent_app_number] => 939951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3084675 [patent_doc_number] => 05284796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Process for flip chip connecting a semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 7/939695 [patent_app_country] => US [patent_app_date] => 1992-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3251 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/284/05284796.pdf [firstpage_image] =>[orig_patent_app_number] => 939695 [rel_patent_id] =>[rel_patent_doc_number] =>)