Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3064579 [patent_doc_number] => 05352629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules' [patent_app_type] => 1 [patent_app_number] => 8/006297 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2555 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/352/05352629.pdf [firstpage_image] =>[orig_patent_app_number] => 006297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/006297
Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules Jan 18, 1993 Issued
Array ( [id] => 3061779 [patent_doc_number] => 05310701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Method for fixing semiconductor bodies on a substrate using wires' [patent_app_type] => 1 [patent_app_number] => 8/003539 [patent_app_country] => US [patent_app_date] => 1993-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1267 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/310/05310701.pdf [firstpage_image] =>[orig_patent_app_number] => 003539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/003539
Method for fixing semiconductor bodies on a substrate using wires Jan 12, 1993 Issued
Array ( [id] => 3611555 [patent_doc_number] => 05565378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Process of passivating a semiconductor device bonding pad by immersion in O.sub.2 or O.sub.3 solution' [patent_app_type] => 1 [patent_app_number] => 7/997833 [patent_app_country] => US [patent_app_date] => 1992-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 6710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565378.pdf [firstpage_image] =>[orig_patent_app_number] => 997833 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/997833
Process of passivating a semiconductor device bonding pad by immersion in O.sub.2 or O.sub.3 solution Dec 28, 1992 Issued
Array ( [id] => 3113353 [patent_doc_number] => 05409866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe' [patent_app_type] => 1 [patent_app_number] => 7/996589 [patent_app_country] => US [patent_app_date] => 1992-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 74 [patent_no_of_words] => 11564 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/409/05409866.pdf [firstpage_image] =>[orig_patent_app_number] => 996589 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996589
Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe Dec 23, 1992 Issued
Array ( [id] => 3083549 [patent_doc_number] => 05279991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Method for fabricating stacks of IC chips by segmenting a larger stack' [patent_app_type] => 1 [patent_app_number] => 7/996794 [patent_app_country] => US [patent_app_date] => 1992-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6824 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/279/05279991.pdf [firstpage_image] =>[orig_patent_app_number] => 996794 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996794
Method for fabricating stacks of IC chips by segmenting a larger stack Dec 23, 1992 Issued
07/987867 ELECTRONIC PACKAGE SEALED WITH A DISPENSABLE ADHESIVE Dec 8, 1992 Abandoned
07/983809 CIRCUIT SUBSTRATE CONNECTION METHOD Nov 23, 1992 Abandoned
07/979299 UNIVERSAL DIE SIZE INNER LEAD LAYOUT AND METHOD OF FORMING A SEMICONDUCTOR DEVICE ASSEMBLY Nov 19, 1992 Abandoned
Array ( [id] => 3024125 [patent_doc_number] => 05316787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Method for manufacturing electrically isolated polyimide coated vias in a flexible substrate' [patent_app_type] => 1 [patent_app_number] => 7/978309 [patent_app_country] => US [patent_app_date] => 1992-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/316/05316787.pdf [firstpage_image] =>[orig_patent_app_number] => 978309 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/978309
Method for manufacturing electrically isolated polyimide coated vias in a flexible substrate Nov 16, 1992 Issued
Array ( [id] => 2893686 [patent_doc_number] => 05272113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'Method for minimizing stress between semiconductor chips having a coefficient of thermal expansion different from that of a mounting substrate' [patent_app_type] => 1 [patent_app_number] => 7/974567 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3138 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272113.pdf [firstpage_image] =>[orig_patent_app_number] => 974567 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/974567
Method for minimizing stress between semiconductor chips having a coefficient of thermal expansion different from that of a mounting substrate Nov 11, 1992 Issued
Array ( [id] => 3034036 [patent_doc_number] => 05300459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Method for reducing thermal stress in an encapsulated integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 7/971329 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300459.pdf [firstpage_image] =>[orig_patent_app_number] => 971329 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/971329
Method for reducing thermal stress in an encapsulated integrated circuit package Nov 3, 1992 Issued
Array ( [id] => 2974511 [patent_doc_number] => 05256562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method for manufacturing a semiconductor device using a circuit transfer film' [patent_app_type] => 1 [patent_app_number] => 7/970675 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 5003 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/256/05256562.pdf [firstpage_image] =>[orig_patent_app_number] => 970675 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/970675
Method for manufacturing a semiconductor device using a circuit transfer film Nov 3, 1992 Issued
Array ( [id] => 2953907 [patent_doc_number] => 05264002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Method for conveying semiconductor lead frame strip with an apparatus having vertically movable guide rails' [patent_app_type] => 1 [patent_app_number] => 7/969384 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2567 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/264/05264002.pdf [firstpage_image] =>[orig_patent_app_number] => 969384 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/969384
Method for conveying semiconductor lead frame strip with an apparatus having vertically movable guide rails Oct 29, 1992 Issued
Array ( [id] => 4365422 [patent_doc_number] => 06274391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'HDI land grid array packaged device having electrical and optical interconnects' [patent_app_type] => 1 [patent_app_number] => 7/966645 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 7336 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274391.pdf [firstpage_image] =>[orig_patent_app_number] => 966645 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966645
HDI land grid array packaged device having electrical and optical interconnects Oct 25, 1992 Issued
Array ( [id] => 3442057 [patent_doc_number] => 05387265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Semiconductor wafer reaction furnace with wafer transfer means' [patent_app_type] => 1 [patent_app_number] => 7/966721 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387265.pdf [firstpage_image] =>[orig_patent_app_number] => 966721 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966721
Semiconductor wafer reaction furnace with wafer transfer means Oct 25, 1992 Issued
Array ( [id] => 3446374 [patent_doc_number] => 05387547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Process for adjusting the impedance of a microwave conductor using an air bridge' [patent_app_type] => 1 [patent_app_number] => 7/965319 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3000 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387547.pdf [firstpage_image] =>[orig_patent_app_number] => 965319 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/965319
Process for adjusting the impedance of a microwave conductor using an air bridge Oct 22, 1992 Issued
Array ( [id] => 2894306 [patent_doc_number] => 05244840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method for manufacturing an encapsulated IC card having a molded frame and a circuit board' [patent_app_type] => 1 [patent_app_number] => 7/963699 [patent_app_country] => US [patent_app_date] => 1992-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 4628 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244840.pdf [firstpage_image] =>[orig_patent_app_number] => 963699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/963699
Method for manufacturing an encapsulated IC card having a molded frame and a circuit board Oct 19, 1992 Issued
07/962117 SEMICONDUCTOR DEVICE HAVING RADIATOR STRUCTURE AND METHOD OF PRODUCING THE SAME Oct 15, 1992 Abandoned
07/958637 TAB TAPE AND MANUFACTURING METHOD THEREFOR Oct 8, 1992 Abandoned
07/954515 SYSTEM AND METHOD FOR ALIGNMENT OF INTEGRATED CIRCUITS MULTIPLE LAYERS Sep 29, 1992 Abandoned
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