David E. Graybill

Array ( [id] => 2989421 [patent_doc_number] => 05346857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for forming a flip-chip bond from a gold-tin eutectic' [patent_app_type] => 1 [patent_app_number] => 7/952005 [patent_app_country] => US [patent_app_date] => 1992-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346857.pdf [firstpage_image] =>[orig_patent_app_number] => 952005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2916619 [patent_doc_number] => 05206186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method for forming semiconductor electrical contacts using metal foil and thermocompression bonding' [patent_app_type] => 1 [patent_app_number] => 7/950553 [patent_app_country] => US [patent_app_date] => 1992-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3063 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206186.pdf [firstpage_image] =>[orig_patent_app_number] => 950553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3052287 [patent_doc_number] => 05344795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Method for encapsulating an integrated circuit using a removable heatsink support block' [patent_app_type] => 1 [patent_app_number] => 7/949189 [patent_app_country] => US [patent_app_date] => 1992-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3453 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/344/05344795.pdf [firstpage_image] =>[orig_patent_app_number] => 949189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3086233 [patent_doc_number] => 05278098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Method for self-aligned polysilicon contact formation' [patent_app_type] => 1 [patent_app_number] => 7/939951 [patent_app_country] => US [patent_app_date] => 1992-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3975 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278098.pdf [firstpage_image] =>[orig_patent_app_number] => 939951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3084675 [patent_doc_number] => 05284796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Process for flip chip connecting a semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 7/939695 [patent_app_country] => US [patent_app_date] => 1992-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3251 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/284/05284796.pdf [firstpage_image] =>[orig_patent_app_number] => 939695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006931 [patent_doc_number] => 05332405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Apparatus for manufacturing semiconductor lead frames in a circular path' [patent_app_type] => 1 [patent_app_number] => 7/938931 [patent_app_country] => US [patent_app_date] => 1992-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2927 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332405.pdf [firstpage_image] =>[orig_patent_app_number] => 938931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2887867 [patent_doc_number] => 05240588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Method for electroplating the lead pins of a semiconductor device pin grid array package' [patent_app_type] => 1 [patent_app_number] => 7/936271 [patent_app_country] => US [patent_app_date] => 1992-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2336 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/240/05240588.pdf [firstpage_image] =>[orig_patent_app_number] => 936271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122323 [patent_doc_number] => 05384286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Process for encapsulating a semiconductor chip, leadframe and heatsink' [patent_app_type] => 1 [patent_app_number] => 7/928285 [patent_app_country] => US [patent_app_date] => 1992-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384286.pdf [firstpage_image] =>[orig_patent_app_number] => 928285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2953138 [patent_doc_number] => 05231036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Method of using a contamination shield during the manufacture of EPROM semiconductor package windows' [patent_app_type] => 1 [patent_app_number] => 7/924309 [patent_app_country] => US [patent_app_date] => 1992-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2143 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231036.pdf [firstpage_image] =>[orig_patent_app_number] => 924309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2994206 [patent_doc_number] => 05362681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Method for separating circuit dies from a wafer' [patent_app_type] => 1 [patent_app_number] => 7/918665 [patent_app_country] => US [patent_app_date] => 1992-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6418 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362681.pdf [firstpage_image] =>[orig_patent_app_number] => 918665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2941941 [patent_doc_number] => 05254500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Method for making an integrally molded semiconductor device heat sink' [patent_app_type] => 1 [patent_app_number] => 7/908987 [patent_app_country] => US [patent_app_date] => 1992-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4091 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/254/05254500.pdf [firstpage_image] =>[orig_patent_app_number] => 908987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2933141 [patent_doc_number] => 05229328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method for bonding dielectric mounted conductors to semiconductor chip contact pads' [patent_app_type] => 1 [patent_app_number] => 7/908429 [patent_app_country] => US [patent_app_date] => 1992-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229328.pdf [firstpage_image] =>[orig_patent_app_number] => 908429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2958329 [patent_doc_number] => 05198391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Method for bonding LLCCC-components using a leadframe' [patent_app_type] => 1 [patent_app_number] => 7/897933 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 970 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198391.pdf [firstpage_image] =>[orig_patent_app_number] => 897933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3091789 [patent_doc_number] => 05290732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Process for making semiconductor electrode bumps by metal cluster ion deposition and etching' [patent_app_type] => 1 [patent_app_number] => 7/896126 [patent_app_country] => US [patent_app_date] => 1992-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 35 [patent_no_of_words] => 7214 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290732.pdf [firstpage_image] =>[orig_patent_app_number] => 896126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3094078 [patent_doc_number] => 05298464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method of mounting a tape automated bonded semiconductor in a housing using a compressor' [patent_app_type] => 1 [patent_app_number] => 7/890984 [patent_app_country] => US [patent_app_date] => 1992-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4322 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298464.pdf [firstpage_image] =>[orig_patent_app_number] => 890984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3091379 [patent_doc_number] => 05290710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method for testing integrated circuits on a carrier substrate' [patent_app_type] => 1 [patent_app_number] => 7/887995 [patent_app_country] => US [patent_app_date] => 1992-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4699 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290710.pdf [firstpage_image] =>[orig_patent_app_number] => 887995 [rel_patent_id] =>[rel_patent_doc_number] =>)