| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2999951
[patent_doc_number] => 05371044
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[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Method of uniformly encapsulating a semiconductor device in resin'
[patent_app_type] => 1
[patent_app_number] => 7/876349
[patent_app_country] => US
[patent_app_date] => 1992-04-30
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[pdf_file] => patents/05/371/05371044.pdf
[firstpage_image] =>[orig_patent_app_number] => 876349
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/876349 | Method of uniformly encapsulating a semiconductor device in resin | Apr 29, 1992 | Issued |
Array
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[id] => 3063530
[patent_doc_number] => 05336272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Method for molding a semiconductor package on a continuous leadframe'
[patent_app_type] => 1
[patent_app_number] => 7/876306
[patent_app_country] => US
[patent_app_date] => 1992-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/336/05336272.pdf
[firstpage_image] =>[orig_patent_app_number] => 876306
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/876306 | Method for molding a semiconductor package on a continuous leadframe | Apr 29, 1992 | Issued |
Array
(
[id] => 3086351
[patent_doc_number] => 05278104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Semiconductor wafer carrier having a dust cover'
[patent_app_type] => 1
[patent_app_number] => 7/870240
[patent_app_country] => US
[patent_app_date] => 1992-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/278/05278104.pdf
[firstpage_image] =>[orig_patent_app_number] => 870240
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/870240 | Semiconductor wafer carrier having a dust cover | Apr 19, 1992 | Issued |
Array
(
[id] => 3093490
[patent_doc_number] => 05369059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Method for constructing a reduced capacitance chip carrier'
[patent_app_type] => 1
[patent_app_number] => 7/865675
[patent_app_country] => US
[patent_app_date] => 1992-04-08
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[pdf_file] => patents/05/369/05369059.pdf
[firstpage_image] =>[orig_patent_app_number] => 865675
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/865675 | Method for constructing a reduced capacitance chip carrier | Apr 7, 1992 | Issued |
Array
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[id] => 2977690
[patent_doc_number] => 05266119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-30
[patent_title] => 'Vacuum sealing mechanism for a semiconductor device manufacturing apparatus having inner and outer bellows'
[patent_app_type] => 1
[patent_app_number] => 7/854875
[patent_app_country] => US
[patent_app_date] => 1992-03-23
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[firstpage_image] =>[orig_patent_app_number] => 854875
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/854875 | Vacuum sealing mechanism for a semiconductor device manufacturing apparatus having inner and outer bellows | Mar 22, 1992 | Issued |
Array
(
[id] => 2935615
[patent_doc_number] => 05254172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Rotating furnace tube having a non-rotating slidable work holder for processing semiconductor substrates'
[patent_app_type] => 1
[patent_app_number] => 7/854037
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[patent_app_date] => 1992-03-19
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[firstpage_image] =>[orig_patent_app_number] => 854037
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/854037 | Rotating furnace tube having a non-rotating slidable work holder for processing semiconductor substrates | Mar 18, 1992 | Issued |
| 07/851755 | IC CHIP PACKAGE AND METHOD OF MAKING SAME | Mar 15, 1992 | Abandoned |
Array
(
[id] => 2967729
[patent_doc_number] => 05258331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars'
[patent_app_type] => 1
[patent_app_number] => 7/852457
[patent_app_country] => US
[patent_app_date] => 1992-03-16
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[pdf_file] => patents/05/258/05258331.pdf
[firstpage_image] =>[orig_patent_app_number] => 852457
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/852457 | Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars | Mar 15, 1992 | Issued |
Array
(
[id] => 2967625
[patent_doc_number] => 05258325
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'Method for manufacturing a semiconductor device using a circuit transfer film'
[patent_app_type] => 1
[patent_app_number] => 7/834849
[patent_app_country] => US
[patent_app_date] => 1992-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/05/258/05258325.pdf
[firstpage_image] =>[orig_patent_app_number] => 834849
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/834849 | Method for manufacturing a semiconductor device using a circuit transfer film | Feb 12, 1992 | Issued |
| 07/835731 | METHOD FOR FORMING A METAL CONTACT | Feb 10, 1992 | Abandoned |
Array
(
[id] => 3083249
[patent_doc_number] => 05279975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Method of testing individual dies on semiconductor wafers prior to singulation'
[patent_app_type] => 1
[patent_app_number] => 7/832785
[patent_app_country] => US
[patent_app_date] => 1992-02-07
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[firstpage_image] =>[orig_patent_app_number] => 832785
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/832785 | Method of testing individual dies on semiconductor wafers prior to singulation | Feb 6, 1992 | Issued |
Array
(
[id] => 2982549
[patent_doc_number] => 05250470
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Method for manufacturing a semiconductor device with corrosion resistant leads'
[patent_app_type] => 1
[patent_app_number] => 7/826689
[patent_app_country] => US
[patent_app_date] => 1992-01-29
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[pdf_file] => patents/05/250/05250470.pdf
[firstpage_image] =>[orig_patent_app_number] => 826689
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/826689 | Method for manufacturing a semiconductor device with corrosion resistant leads | Jan 28, 1992 | Issued |
| 07/824238 | METHOD FOR FORMING A METAL CONTACT | Jan 20, 1992 | Abandoned |
Array
(
[id] => 3036271
[patent_doc_number] => 05286296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Multi-chamber wafer process equipment having plural, physically communicating transfer means'
[patent_app_type] => 1
[patent_app_number] => 7/818535
[patent_app_country] => US
[patent_app_date] => 1992-01-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/286/05286296.pdf
[firstpage_image] =>[orig_patent_app_number] => 818535
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/818535 | Multi-chamber wafer process equipment having plural, physically communicating transfer means | Jan 8, 1992 | Issued |
Array
(
[id] => 2784990
[patent_doc_number] => 05155068
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[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal'
[patent_app_type] => 1
[patent_app_number] => 7/818469
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[firstpage_image] =>[orig_patent_app_number] => 818469
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Array
(
[id] => 2926992
[patent_doc_number] => 05187123
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[patent_kind] => NA
[patent_issue_date] => 1993-02-16
[patent_title] => 'Method for bonding a semiconductor device to a lead frame die pad using plural adhesive spots'
[patent_app_type] => 1
[patent_app_number] => 7/815621
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[patent_app_date] => 1991-12-30
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[firstpage_image] =>[orig_patent_app_number] => 815621
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/815621 | Method for bonding a semiconductor device to a lead frame die pad using plural adhesive spots | Dec 29, 1991 | Issued |
Array
(
[id] => 2933069
[patent_doc_number] => 05229324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-20
[patent_title] => 'Method for forming contacts to p-type HgCdTe semiconductor material using lead and tin'
[patent_app_type] => 1
[patent_app_number] => 7/813249
[patent_app_country] => US
[patent_app_date] => 1991-12-23
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[pdf_file] => patents/05/229/05229324.pdf
[firstpage_image] =>[orig_patent_app_number] => 813249
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/813249 | Method for forming contacts to p-type HgCdTe semiconductor material using lead and tin | Dec 22, 1991 | Issued |
Array
(
[id] => 2931489
[patent_doc_number] => 05188982
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[patent_kind] => NA
[patent_issue_date] => 1993-02-23
[patent_title] => 'Method of bonding a semiconductor die to a package using a gold/silicon preform and cooling the die and package through a monotonically decreasing temperature sequence'
[patent_app_type] => 1
[patent_app_number] => 7/811495
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/811495 | Method of bonding a semiconductor die to a package using a gold/silicon preform and cooling the die and package through a monotonically decreasing temperature sequence | Dec 19, 1991 | Issued |
Array
(
[id] => 2839384
[patent_doc_number] => 05171712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-15
[patent_title] => 'Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate'
[patent_app_type] => 1
[patent_app_number] => 7/811755
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/811755 | Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate | Dec 19, 1991 | Issued |
Array
(
[id] => 2899107
[patent_doc_number] => 05217922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-08
[patent_title] => 'Method for forming a silicide layer and barrier layer on a semiconductor device rear surface'
[patent_app_type] => 1
[patent_app_number] => 7/810313
[patent_app_country] => US
[patent_app_date] => 1991-12-19
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[firstpage_image] =>[orig_patent_app_number] => 810313
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/810313 | Method for forming a silicide layer and barrier layer on a semiconductor device rear surface | Dec 18, 1991 | Issued |