| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1994-05-10
[patent_title] => 'Method for processing semi-conductor wafers in a multiple vacuum and non-vacuum chamber apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/807162
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[patent_app_date] => 1991-12-13
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[pdf_file] => patents/05/310/05310410.pdf
[firstpage_image] =>[orig_patent_app_number] => 807162
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/807162 | Method for processing semi-conductor wafers in a multiple vacuum and non-vacuum chamber apparatus | Dec 12, 1991 | Issued |
Array
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[id] => 2986186
[patent_doc_number] => 05212115
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-18
[patent_title] => 'Method for microelectronic device packaging employing capacitively coupled connections'
[patent_app_type] => 1
[patent_app_number] => 7/802929
[patent_app_country] => US
[patent_app_date] => 1991-12-06
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[pdf_file] => patents/05/212/05212115.pdf
[firstpage_image] =>[orig_patent_app_number] => 802929
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/802929 | Method for microelectronic device packaging employing capacitively coupled connections | Dec 5, 1991 | Issued |
Array
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[id] => 2921066
[patent_doc_number] => 05200363
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-06
[patent_title] => 'Method for manufacturing a semiconductor package including a glass support'
[patent_app_type] => 1
[patent_app_number] => 7/830205
[patent_app_country] => US
[patent_app_date] => 1991-11-20
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[pdf_file] => patents/05/200/05200363.pdf
[firstpage_image] =>[orig_patent_app_number] => 830205
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830205 | Method for manufacturing a semiconductor package including a glass support | Nov 19, 1991 | Issued |
Array
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[patent_doc_number] => 05197185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Process of forming electrical connections between conductive layers using thermosonic wire bonded bump vias and thick film techniques'
[patent_app_type] => 1
[patent_app_number] => 7/794097
[patent_app_country] => US
[patent_app_date] => 1991-11-18
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[pdf_file] => patents/05/197/05197185.pdf
[firstpage_image] =>[orig_patent_app_number] => 794097
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/794097 | Process of forming electrical connections between conductive layers using thermosonic wire bonded bump vias and thick film techniques | Nov 17, 1991 | Issued |
Array
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[id] => 2894273
[patent_doc_number] => 05244838
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-14
[patent_title] => 'Process and apparatus for assembling and resin-encapsulating a heat sink-mounted semiconductor power device'
[patent_app_type] => 1
[patent_app_number] => 7/784303
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[patent_app_date] => 1991-10-31
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[firstpage_image] =>[orig_patent_app_number] => 784303
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/784303 | Process and apparatus for assembling and resin-encapsulating a heat sink-mounted semiconductor power device | Oct 30, 1991 | Issued |
Array
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[id] => 2804567
[patent_doc_number] => 05147821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suction in a molding operation'
[patent_app_type] => 1
[patent_app_number] => 7/786205
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Array
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[id] => 2933122
[patent_doc_number] => 05229327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-20
[patent_title] => 'Process for manufacturing semiconductor device structures cooled by Peltier junctions and electrical interconnect assemblies therefor'
[patent_app_type] => 1
[patent_app_number] => 7/781087
[patent_app_country] => US
[patent_app_date] => 1991-10-21
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[pdf_file] => patents/05/229/05229327.pdf
[firstpage_image] =>[orig_patent_app_number] => 781087
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/781087 | Process for manufacturing semiconductor device structures cooled by Peltier junctions and electrical interconnect assemblies therefor | Oct 20, 1991 | Issued |
Array
(
[id] => 3007432
[patent_doc_number] => 05275970
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Method of forming bonding bumps by punching a metal ribbon'
[patent_app_type] => 1
[patent_app_number] => 7/777903
[patent_app_country] => US
[patent_app_date] => 1991-10-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/275/05275970.pdf
[firstpage_image] =>[orig_patent_app_number] => 777903
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/777903 | Method of forming bonding bumps by punching a metal ribbon | Oct 16, 1991 | Issued |
Array
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[id] => 2935273
[patent_doc_number] => 05260234
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Method for bonding a lead to a die pad using an electroless plating solution'
[patent_app_type] => 1
[patent_app_number] => 7/773519
[patent_app_country] => US
[patent_app_date] => 1991-10-09
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[pdf_file] => patents/05/260/05260234.pdf
[firstpage_image] =>[orig_patent_app_number] => 773519
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/773519 | Method for bonding a lead to a die pad using an electroless plating solution | Oct 8, 1991 | Issued |
Array
(
[id] => 2805081
[patent_doc_number] => 05156998
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes'
[patent_app_type] => 1
[patent_app_number] => 7/767949
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[pdf_file] => patents/05/156/05156998.pdf
[firstpage_image] =>[orig_patent_app_number] => 767949
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/767949 | Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes | Sep 29, 1991 | Issued |
Array
(
[id] => 2921102
[patent_doc_number] => 05200365
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-06
[patent_title] => 'System for achieving desired bondlength of adhesive between a semiconductor chip package and a heatsink'
[patent_app_type] => 1
[patent_app_number] => 7/765597
[patent_app_country] => US
[patent_app_date] => 1991-09-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/200/05200365.pdf
[firstpage_image] =>[orig_patent_app_number] => 765597
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/765597 | System for achieving desired bondlength of adhesive between a semiconductor chip package and a heatsink | Sep 25, 1991 | Issued |
| 07/760869 | TESTING AND FINISHING SYSTEM FOR INTEGRATED CIRCUIT PACKAGE UNITS | Sep 15, 1991 | Abandoned |
Array
(
[id] => 2921048
[patent_doc_number] => 05200362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-06
[patent_title] => 'Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film'
[patent_app_type] => 1
[patent_app_number] => 7/756952
[patent_app_country] => US
[patent_app_date] => 1991-09-09
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[firstpage_image] =>[orig_patent_app_number] => 756952
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/756952 | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film | Sep 8, 1991 | Issued |
| 07/753457 | STACKED LEADFRAME ARRAY PACKAGE AND METHOD OF MAKING | Sep 2, 1991 | Abandoned |
Array
(
[id] => 3017918
[patent_doc_number] => 05288667
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'Method of manufacturing a molded semiconductor package having a lead frame and an connecting coupler'
[patent_app_type] => 1
[patent_app_number] => 7/747587
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[patent_app_date] => 1991-08-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/747587 | Method of manufacturing a molded semiconductor package having a lead frame and an connecting coupler | Aug 19, 1991 | Issued |
Array
(
[id] => 2931895
[patent_doc_number] => 05196371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Flip chip bonding method using electrically conductive polymer bumps'
[patent_app_type] => 1
[patent_app_number] => 7/746333
[patent_app_country] => US
[patent_app_date] => 1991-08-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/196/05196371.pdf
[firstpage_image] =>[orig_patent_app_number] => 746333
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/746333 | Flip chip bonding method using electrically conductive polymer bumps | Aug 15, 1991 | Issued |
| 07/737143 | METHOD AND LEADFRAME FOR MAKING ELECTRONIC COMPONENTS | Jul 28, 1991 | Abandoned |
Array
(
[id] => 2948553
[patent_doc_number] => 05262351
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Process for manufacturing a multilayer integrated circuit interconnection'
[patent_app_type] => 1
[patent_app_number] => 7/734671
[patent_app_country] => US
[patent_app_date] => 1991-07-23
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[pdf_file] => patents/05/262/05262351.pdf
[firstpage_image] =>[orig_patent_app_number] => 734671
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/734671 | Process for manufacturing a multilayer integrated circuit interconnection | Jul 22, 1991 | Issued |
Array
(
[id] => 2908000
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'Pressure-reduced chamber system having a filter means'
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[patent_app_number] => 7/732911
[patent_app_country] => US
[patent_app_date] => 1991-07-19
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 732911
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/732911 | Pressure-reduced chamber system having a filter means | Jul 18, 1991 | Issued |
Array
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[id] => 2866190
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Method of making an electrical interconnection having angular lead design'
[patent_app_type] => 1
[patent_app_number] => 7/732289
[patent_app_country] => US
[patent_app_date] => 1991-07-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/732289 | Method of making an electrical interconnection having angular lead design | Jul 17, 1991 | Issued |