Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2931895 [patent_doc_number] => 05196371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Flip chip bonding method using electrically conductive polymer bumps' [patent_app_type] => 1 [patent_app_number] => 7/746333 [patent_app_country] => US [patent_app_date] => 1991-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196371.pdf [firstpage_image] =>[orig_patent_app_number] => 746333 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/746333
Flip chip bonding method using electrically conductive polymer bumps Aug 15, 1991 Issued
07/737143 METHOD AND LEADFRAME FOR MAKING ELECTRONIC COMPONENTS Jul 28, 1991 Abandoned
Array ( [id] => 2948553 [patent_doc_number] => 05262351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Process for manufacturing a multilayer integrated circuit interconnection' [patent_app_type] => 1 [patent_app_number] => 7/734671 [patent_app_country] => US [patent_app_date] => 1991-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3130 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/262/05262351.pdf [firstpage_image] =>[orig_patent_app_number] => 734671 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/734671
Process for manufacturing a multilayer integrated circuit interconnection Jul 22, 1991 Issued
Array ( [id] => 2908000 [patent_doc_number] => 05178638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Pressure-reduced chamber system having a filter means' [patent_app_type] => 1 [patent_app_number] => 7/732911 [patent_app_country] => US [patent_app_date] => 1991-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3967 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/178/05178638.pdf [firstpage_image] =>[orig_patent_app_number] => 732911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732911
Pressure-reduced chamber system having a filter means Jul 18, 1991 Issued
Array ( [id] => 2866190 [patent_doc_number] => 05162265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Method of making an electrical interconnection having angular lead design' [patent_app_type] => 1 [patent_app_number] => 7/732289 [patent_app_country] => US [patent_app_date] => 1991-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2438 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162265.pdf [firstpage_image] =>[orig_patent_app_number] => 732289 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732289
Method of making an electrical interconnection having angular lead design Jul 17, 1991 Issued
Array ( [id] => 2993350 [patent_doc_number] => 05370709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Semiconductor wafer processing apparatus having a Bernoulli chuck' [patent_app_type] => 1 [patent_app_number] => 7/731321 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6051 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/370/05370709.pdf [firstpage_image] =>[orig_patent_app_number] => 731321 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/731321
Semiconductor wafer processing apparatus having a Bernoulli chuck Jul 16, 1991 Issued
07/729399 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE Jul 11, 1991 Abandoned
Array ( [id] => 2890894 [patent_doc_number] => 05217501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Vertical wafer heat treatment apparatus having dual load lock chambers' [patent_app_type] => 1 [patent_app_number] => 7/729836 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/217/05217501.pdf [firstpage_image] =>[orig_patent_app_number] => 729836 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729836
Vertical wafer heat treatment apparatus having dual load lock chambers Jul 11, 1991 Issued
Array ( [id] => 2799250 [patent_doc_number] => 05139969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Method of making resin molded semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/725895 [patent_app_country] => US [patent_app_date] => 1991-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1005 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139969.pdf [firstpage_image] =>[orig_patent_app_number] => 725895 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/725895
Method of making resin molded semiconductor device Jun 30, 1991 Issued
Array ( [id] => 2848556 [patent_doc_number] => 05104827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method of making a plastic-packaged semiconductor device having lead support and alignment structure' [patent_app_type] => 1 [patent_app_number] => 7/721950 [patent_app_country] => US [patent_app_date] => 1991-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2371 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104827.pdf [firstpage_image] =>[orig_patent_app_number] => 721950 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/721950
Method of making a plastic-packaged semiconductor device having lead support and alignment structure Jun 26, 1991 Issued
07/720307 MICROCONTROLLER AND A METHOD FOR FORMING THE SAME Jun 24, 1991 Abandoned
Array ( [id] => 2848424 [patent_doc_number] => 05104820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting' [patent_app_type] => 1 [patent_app_number] => 7/720025 [patent_app_country] => US [patent_app_date] => 1991-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7577 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104820.pdf [firstpage_image] =>[orig_patent_app_number] => 720025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/720025
Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting Jun 23, 1991 Issued
07/717033 PROCESS FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT STAGE Jun 17, 1991 Abandoned
Array ( [id] => 2793079 [patent_doc_number] => 05143855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Method for making contact openings in color image sensor passivation layer' [patent_app_type] => 1 [patent_app_number] => 7/716445 [patent_app_country] => US [patent_app_date] => 1991-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2505 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/143/05143855.pdf [firstpage_image] =>[orig_patent_app_number] => 716445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/716445
Method for making contact openings in color image sensor passivation layer Jun 16, 1991 Issued
07/713093 METHOD OF MAKING A CARRIER ELEMENT FOR INCORPORATION IN AN IDENTITY CARD Jun 10, 1991 Abandoned
07/713589 LOW RESISTANCE CONTACTS BETWEEN SILICIDED AREAS AND UPPER LEVEL POLYSILICON INTERCONNECT Jun 5, 1991 Abandoned
Array ( [id] => 2916516 [patent_doc_number] => 05206181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing' [patent_app_type] => 1 [patent_app_number] => 7/709553 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2641 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206181.pdf [firstpage_image] =>[orig_patent_app_number] => 709553 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709553
Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing Jun 2, 1991 Issued
Array ( [id] => 2967000 [patent_doc_number] => 05202289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method of plastically deforming a semiconductor device lead frame in preparation for ultrasonic bonding' [patent_app_type] => 1 [patent_app_number] => 7/706823 [patent_app_country] => US [patent_app_date] => 1991-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2019 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202289.pdf [firstpage_image] =>[orig_patent_app_number] => 706823 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/706823
Method of plastically deforming a semiconductor device lead frame in preparation for ultrasonic bonding May 28, 1991 Issued
Array ( [id] => 2823170 [patent_doc_number] => 05169805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of resiliently mounting an integrated circuit chip to enable conformal heat dissipation' [patent_app_type] => 1 [patent_app_number] => 7/706637 [patent_app_country] => US [patent_app_date] => 1991-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169805.pdf [firstpage_image] =>[orig_patent_app_number] => 706637 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/706637
Method of resiliently mounting an integrated circuit chip to enable conformal heat dissipation May 28, 1991 Issued
Array ( [id] => 2840100 [patent_doc_number] => 05137836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Method of manufacturing a repairable multi-chip module' [patent_app_type] => 1 [patent_app_number] => 7/704941 [patent_app_country] => US [patent_app_date] => 1991-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2908 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/137/05137836.pdf [firstpage_image] =>[orig_patent_app_number] => 704941 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704941
Method of manufacturing a repairable multi-chip module May 22, 1991 Issued
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