Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2993350 [patent_doc_number] => 05370709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Semiconductor wafer processing apparatus having a Bernoulli chuck' [patent_app_type] => 1 [patent_app_number] => 7/731321 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6051 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/370/05370709.pdf [firstpage_image] =>[orig_patent_app_number] => 731321 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/731321
Semiconductor wafer processing apparatus having a Bernoulli chuck Jul 16, 1991 Issued
07/729399 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE Jul 11, 1991 Abandoned
Array ( [id] => 2890894 [patent_doc_number] => 05217501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Vertical wafer heat treatment apparatus having dual load lock chambers' [patent_app_type] => 1 [patent_app_number] => 7/729836 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/217/05217501.pdf [firstpage_image] =>[orig_patent_app_number] => 729836 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729836
Vertical wafer heat treatment apparatus having dual load lock chambers Jul 11, 1991 Issued
Array ( [id] => 2799250 [patent_doc_number] => 05139969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Method of making resin molded semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/725895 [patent_app_country] => US [patent_app_date] => 1991-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1005 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139969.pdf [firstpage_image] =>[orig_patent_app_number] => 725895 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/725895
Method of making resin molded semiconductor device Jun 30, 1991 Issued
Array ( [id] => 2848556 [patent_doc_number] => 05104827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method of making a plastic-packaged semiconductor device having lead support and alignment structure' [patent_app_type] => 1 [patent_app_number] => 7/721950 [patent_app_country] => US [patent_app_date] => 1991-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2371 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104827.pdf [firstpage_image] =>[orig_patent_app_number] => 721950 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/721950
Method of making a plastic-packaged semiconductor device having lead support and alignment structure Jun 26, 1991 Issued
07/720307 MICROCONTROLLER AND A METHOD FOR FORMING THE SAME Jun 24, 1991 Abandoned
Array ( [id] => 2848424 [patent_doc_number] => 05104820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting' [patent_app_type] => 1 [patent_app_number] => 7/720025 [patent_app_country] => US [patent_app_date] => 1991-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7577 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104820.pdf [firstpage_image] =>[orig_patent_app_number] => 720025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/720025
Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting Jun 23, 1991 Issued
07/717033 PROCESS FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT STAGE Jun 17, 1991 Abandoned
Array ( [id] => 2793079 [patent_doc_number] => 05143855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Method for making contact openings in color image sensor passivation layer' [patent_app_type] => 1 [patent_app_number] => 7/716445 [patent_app_country] => US [patent_app_date] => 1991-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2505 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/143/05143855.pdf [firstpage_image] =>[orig_patent_app_number] => 716445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/716445
Method for making contact openings in color image sensor passivation layer Jun 16, 1991 Issued
07/713093 METHOD OF MAKING A CARRIER ELEMENT FOR INCORPORATION IN AN IDENTITY CARD Jun 10, 1991 Abandoned
07/713589 LOW RESISTANCE CONTACTS BETWEEN SILICIDED AREAS AND UPPER LEVEL POLYSILICON INTERCONNECT Jun 5, 1991 Abandoned
Array ( [id] => 2916516 [patent_doc_number] => 05206181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing' [patent_app_type] => 1 [patent_app_number] => 7/709553 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2641 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206181.pdf [firstpage_image] =>[orig_patent_app_number] => 709553 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709553
Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing Jun 2, 1991 Issued
Array ( [id] => 2967000 [patent_doc_number] => 05202289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method of plastically deforming a semiconductor device lead frame in preparation for ultrasonic bonding' [patent_app_type] => 1 [patent_app_number] => 7/706823 [patent_app_country] => US [patent_app_date] => 1991-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2019 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202289.pdf [firstpage_image] =>[orig_patent_app_number] => 706823 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/706823
Method of plastically deforming a semiconductor device lead frame in preparation for ultrasonic bonding May 28, 1991 Issued
Array ( [id] => 2823170 [patent_doc_number] => 05169805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of resiliently mounting an integrated circuit chip to enable conformal heat dissipation' [patent_app_type] => 1 [patent_app_number] => 7/706637 [patent_app_country] => US [patent_app_date] => 1991-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169805.pdf [firstpage_image] =>[orig_patent_app_number] => 706637 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/706637
Method of resiliently mounting an integrated circuit chip to enable conformal heat dissipation May 28, 1991 Issued
Array ( [id] => 2840100 [patent_doc_number] => 05137836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Method of manufacturing a repairable multi-chip module' [patent_app_type] => 1 [patent_app_number] => 7/704941 [patent_app_country] => US [patent_app_date] => 1991-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2908 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/137/05137836.pdf [firstpage_image] =>[orig_patent_app_number] => 704941 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704941
Method of manufacturing a repairable multi-chip module May 22, 1991 Issued
Array ( [id] => 2778697 [patent_doc_number] => 05154730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Semiconductor wafer processing module having an inclined rotating wafer handling turret and a method of using the module' [patent_app_type] => 1 [patent_app_number] => 7/701771 [patent_app_country] => US [patent_app_date] => 1991-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4893 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/154/05154730.pdf [firstpage_image] =>[orig_patent_app_number] => 701771 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/701771
Semiconductor wafer processing module having an inclined rotating wafer handling turret and a method of using the module May 16, 1991 Issued
Array ( [id] => 3009566 [patent_doc_number] => 05281556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Process for manufacturing a multi-layer lead frame having a ground plane and a power supply plane' [patent_app_type] => 1 [patent_app_number] => 7/701183 [patent_app_country] => US [patent_app_date] => 1991-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3088 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281556.pdf [firstpage_image] =>[orig_patent_app_number] => 701183 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/701183
Process for manufacturing a multi-layer lead frame having a ground plane and a power supply plane May 15, 1991 Issued
Array ( [id] => 2916657 [patent_doc_number] => 05206188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method of manufacturing a high lead count circuit board' [patent_app_type] => 1 [patent_app_number] => 7/700251 [patent_app_country] => US [patent_app_date] => 1991-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3000 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206188.pdf [firstpage_image] =>[orig_patent_app_number] => 700251 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/700251
Method of manufacturing a high lead count circuit board May 14, 1991 Issued
Array ( [id] => 2920622 [patent_doc_number] => 05192682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Manufacturing method for thin semiconductor device assemblies' [patent_app_type] => 1 [patent_app_number] => 7/697963 [patent_app_country] => US [patent_app_date] => 1991-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1705 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/192/05192682.pdf [firstpage_image] =>[orig_patent_app_number] => 697963 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/697963
Manufacturing method for thin semiconductor device assemblies May 9, 1991 Issued
Array ( [id] => 2812416 [patent_doc_number] => 05086018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Method of making a planarized thin film covered wire bonded semiconductor package' [patent_app_type] => 1 [patent_app_number] => 7/694719 [patent_app_country] => US [patent_app_date] => 1991-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2986 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086018.pdf [firstpage_image] =>[orig_patent_app_number] => 694719 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/694719
Method of making a planarized thin film covered wire bonded semiconductor package May 1, 1991 Issued
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