Search

David E. Graybill

Examiner (ID: 8531)

Most Active Art Unit
2894
Art Unit(s)
1763, 3727, 2894, 1107, 2822, 2812, 2814, 2827
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
07/691627 INTEGRATED CIRCUIT PACKAGING USING FLEXIBLE SUBSTRATE Apr 24, 1991 Abandoned
Array ( [id] => 2919185 [patent_doc_number] => 05186719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Apparatus for conveying semiconductor lead frame strip using guide rails' [patent_app_type] => 1 [patent_app_number] => 7/688295 [patent_app_country] => US [patent_app_date] => 1991-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2569 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/186/05186719.pdf [firstpage_image] =>[orig_patent_app_number] => 688295 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/688295
Apparatus for conveying semiconductor lead frame strip using guide rails Apr 21, 1991 Issued
07/690171 METHOD OF DEPOSITING CONDUCTORS IN HIGH ASPECT RATIO APERTURES Apr 18, 1991 Abandoned
Array ( [id] => 2807627 [patent_doc_number] => 05140404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape' [patent_app_type] => 1 [patent_app_number] => 7/688023 [patent_app_country] => US [patent_app_date] => 1991-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2999 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140404.pdf [firstpage_image] =>[orig_patent_app_number] => 688023 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/688023
Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape Apr 18, 1991 Issued
Array ( [id] => 2919163 [patent_doc_number] => 05186718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Staged-vacuum wafer processing system and method' [patent_app_type] => 1 [patent_app_number] => 7/685976 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2766 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/186/05186718.pdf [firstpage_image] =>[orig_patent_app_number] => 685976 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/685976
Staged-vacuum wafer processing system and method Apr 14, 1991 Issued
Array ( [id] => 2894182 [patent_doc_number] => 05244833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer' [patent_app_type] => 1 [patent_app_number] => 7/683893 [patent_app_country] => US [patent_app_date] => 1991-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244833.pdf [firstpage_image] =>[orig_patent_app_number] => 683893 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/683893
Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer Apr 10, 1991 Issued
07/679525 ELECTRONIC SUBSTRATE MULTIPLE LOCATION CONDUCTOR ATTACHMENT TECHNOLOGY Apr 1, 1991 Abandoned
Array ( [id] => 2834170 [patent_doc_number] => 05120665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits' [patent_app_type] => 1 [patent_app_number] => 7/671472 [patent_app_country] => US [patent_app_date] => 1991-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 11027 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/120/05120665.pdf [firstpage_image] =>[orig_patent_app_number] => 671472 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/671472
Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits Mar 18, 1991 Issued
Array ( [id] => 2854951 [patent_doc_number] => 05166098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Method of manufacturing an encapsulated semiconductor device with a can type housing' [patent_app_type] => 1 [patent_app_number] => 7/652967 [patent_app_country] => US [patent_app_date] => 1991-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3087 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166098.pdf [firstpage_image] =>[orig_patent_app_number] => 652967 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/652967
Method of manufacturing an encapsulated semiconductor device with a can type housing Mar 10, 1991 Issued
07/665253 STRUCTURE AND METHOD FOR SELF-ALIGNED CONTACT FORMATION Mar 4, 1991 Abandoned
Array ( [id] => 2804454 [patent_doc_number] => 05147815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Method for fabricating a multichip semiconductor device having two interdigitated leadframes' [patent_app_type] => 1 [patent_app_number] => 7/663223 [patent_app_country] => US [patent_app_date] => 1991-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3659 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147815.pdf [firstpage_image] =>[orig_patent_app_number] => 663223 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/663223
Method for fabricating a multichip semiconductor device having two interdigitated leadframes Feb 28, 1991 Issued
Array ( [id] => 2828374 [patent_doc_number] => 05175060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same' [patent_app_type] => 1 [patent_app_number] => 7/663933 [patent_app_country] => US [patent_app_date] => 1991-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 48 [patent_no_of_words] => 7381 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175060.pdf [firstpage_image] =>[orig_patent_app_number] => 663933 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/663933
Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same Feb 28, 1991 Issued
Array ( [id] => 2771793 [patent_doc_number] => 05075255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Method of removing contaminants from a plated article with a clean burning hydrogen flame' [patent_app_type] => 1 [patent_app_number] => 7/661143 [patent_app_country] => US [patent_app_date] => 1991-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1707 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075255.pdf [firstpage_image] =>[orig_patent_app_number] => 661143 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/661143
Method of removing contaminants from a plated article with a clean burning hydrogen flame Feb 26, 1991 Issued
Array ( [id] => 2953446 [patent_doc_number] => 05231052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Process for forming a multilayer polysilicon semiconductor electrode' [patent_app_type] => 1 [patent_app_number] => 7/655123 [patent_app_country] => US [patent_app_date] => 1991-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2227 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231052.pdf [firstpage_image] =>[orig_patent_app_number] => 655123 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655123
Process for forming a multilayer polysilicon semiconductor electrode Feb 13, 1991 Issued
Array ( [id] => 2805050 [patent_doc_number] => 05156997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-20 [patent_title] => 'Method of making semiconductor bonding bumps using metal cluster ion deposition' [patent_app_type] => 1 [patent_app_number] => 7/653609 [patent_app_country] => US [patent_app_date] => 1991-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/156/05156997.pdf [firstpage_image] =>[orig_patent_app_number] => 653609 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/653609
Method of making semiconductor bonding bumps using metal cluster ion deposition Feb 10, 1991 Issued
Array ( [id] => 2882276 [patent_doc_number] => 05108955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Method of making a resin encapsulated pin grid array with integral heatsink' [patent_app_type] => 1 [patent_app_number] => 7/652191 [patent_app_country] => US [patent_app_date] => 1991-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 5616 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/108/05108955.pdf [firstpage_image] =>[orig_patent_app_number] => 652191 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/652191
Method of making a resin encapsulated pin grid array with integral heatsink Feb 5, 1991 Issued
Array ( [id] => 2784705 [patent_doc_number] => 05093282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Method of making a semiconductor device having lead pins and a metal shell' [patent_app_type] => 1 [patent_app_number] => 7/648311 [patent_app_country] => US [patent_app_date] => 1991-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2448 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093282.pdf [firstpage_image] =>[orig_patent_app_number] => 648311 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/648311
Method of making a semiconductor device having lead pins and a metal shell Jan 28, 1991 Issued
Array ( [id] => 2814343 [patent_doc_number] => 05122480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Method for assembling a heat sink to a circuit element using a retentive spring force' [patent_app_type] => 1 [patent_app_number] => 7/627531 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122480.pdf [firstpage_image] =>[orig_patent_app_number] => 627531 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/627531
Method for assembling a heat sink to a circuit element using a retentive spring force Jan 22, 1991 Issued
07/643635 LEADLESS CHIP RESISTOR CAPACITOR CARRIER FOR HYBRID CIRCUITS AND A METHOD OF MAKING THE SAME Jan 21, 1991 Abandoned
Array ( [id] => 2846052 [patent_doc_number] => 05110763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Process of fabricating multi-level wiring structure, incorporated in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/643891 [patent_app_country] => US [patent_app_date] => 1991-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3867 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/110/05110763.pdf [firstpage_image] =>[orig_patent_app_number] => 643891 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/643891
Process of fabricating multi-level wiring structure, incorporated in semiconductor device Jan 21, 1991 Issued
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