David E. Graybill

Array ( [id] => 2882276 [patent_doc_number] => 05108955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Method of making a resin encapsulated pin grid array with integral heatsink' [patent_app_type] => 1 [patent_app_number] => 7/652191 [patent_app_country] => US [patent_app_date] => 1991-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 5616 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/108/05108955.pdf [firstpage_image] =>[orig_patent_app_number] => 652191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2784705 [patent_doc_number] => 05093282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Method of making a semiconductor device having lead pins and a metal shell' [patent_app_type] => 1 [patent_app_number] => 7/648311 [patent_app_country] => US [patent_app_date] => 1991-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2448 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093282.pdf [firstpage_image] =>[orig_patent_app_number] => 648311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2814343 [patent_doc_number] => 05122480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Method for assembling a heat sink to a circuit element using a retentive spring force' [patent_app_type] => 1 [patent_app_number] => 7/627531 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122480.pdf [firstpage_image] =>[orig_patent_app_number] => 627531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2846052 [patent_doc_number] => 05110763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Process of fabricating multi-level wiring structure, incorporated in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/643891 [patent_app_country] => US [patent_app_date] => 1991-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3867 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/110/05110763.pdf [firstpage_image] =>[orig_patent_app_number] => 643891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2958222 [patent_doc_number] => 05198385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Photolithographic formation of die-to-package airbridge in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/640041 [patent_app_country] => US [patent_app_date] => 1991-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1652 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198385.pdf [firstpage_image] =>[orig_patent_app_number] => 640041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2800779 [patent_doc_number] => 05124277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Method of ball bonding to non-wire bonded electrodes of semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/639237 [patent_app_country] => US [patent_app_date] => 1991-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2925 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124277.pdf [firstpage_image] =>[orig_patent_app_number] => 639237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2814251 [patent_doc_number] => 05122475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Method of making a high speed, high density semiconductor memory package with chip level repairability' [patent_app_type] => 1 [patent_app_number] => 7/632089 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4085 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122475.pdf [firstpage_image] =>[orig_patent_app_number] => 632089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3009213 [patent_doc_number] => 05327624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method for forming a thin film on a semiconductor device using an apparatus having a load lock' [patent_app_type] => 1 [patent_app_number] => 7/629566 [patent_app_country] => US [patent_app_date] => 1990-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1726 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327624.pdf [firstpage_image] =>[orig_patent_app_number] => 629566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3478494 [patent_doc_number] => 05399531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Single semiconductor wafer transfer method and plural processing station manufacturing system' [patent_app_type] => 1 [patent_app_number] => 7/628437 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6638 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399531.pdf [firstpage_image] =>[orig_patent_app_number] => 628437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799331 [patent_doc_number] => 05139973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Method for making a semiconductor package with the distance between a lead frame die pad and heat spreader determined by the thickness of an intermediary insulating sheet' [patent_app_type] => 1 [patent_app_number] => 7/628513 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1956 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139973.pdf [firstpage_image] =>[orig_patent_app_number] => 628513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2882201 [patent_doc_number] => 05108951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Method for forming a metal contact' [patent_app_type] => 1 [patent_app_number] => 7/609883 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 2656 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/108/05108951.pdf [firstpage_image] =>[orig_patent_app_number] => 609883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2722947 [patent_doc_number] => 05057441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Method for reliability testing integrated circuit metal films' [patent_app_type] => 1 [patent_app_number] => 7/605043 [patent_app_country] => US [patent_app_date] => 1990-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5078 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057441.pdf [firstpage_image] =>[orig_patent_app_number] => 605043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2891413 [patent_doc_number] => 05177032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape' [patent_app_type] => 1 [patent_app_number] => 7/602990 [patent_app_country] => US [patent_app_date] => 1990-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3001 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177032.pdf [firstpage_image] =>[orig_patent_app_number] => 602990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772253 [patent_doc_number] => 05142756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Apparatus for loading and re-slicing semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/599861 [patent_app_country] => US [patent_app_date] => 1990-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 22 [patent_no_of_words] => 6446 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142756.pdf [firstpage_image] =>[orig_patent_app_number] => 599861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2822812 [patent_doc_number] => 05094969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Method for making a stackable multilayer substrate for mounting integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/594373 [patent_app_country] => US [patent_app_date] => 1990-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1733 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/094/05094969.pdf [firstpage_image] =>[orig_patent_app_number] => 594373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2850782 [patent_doc_number] => 05126286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Method of manufacturing edge connected semiconductor die' [patent_app_type] => 1 [patent_app_number] => 7/593155 [patent_app_country] => US [patent_app_date] => 1990-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126286.pdf [firstpage_image] =>[orig_patent_app_number] => 593155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2860543 [patent_doc_number] => 05082802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-21 [patent_title] => 'Method of making a memory device by packaging two integrated circuit dies in one package' [patent_app_type] => 1 [patent_app_number] => 7/585583 [patent_app_country] => US [patent_app_date] => 1990-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1887 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/082/05082802.pdf [firstpage_image] =>[orig_patent_app_number] => 585583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2766366 [patent_doc_number] => 05063174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-05 [patent_title] => 'Si/Au/Ni alloyed ohmic contact to n-GaAs and fabricating process therefor' [patent_app_type] => 1 [patent_app_number] => 7/585015 [patent_app_country] => US [patent_app_date] => 1990-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3596 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/063/05063174.pdf [firstpage_image] =>[orig_patent_app_number] => 585015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2734772 [patent_doc_number] => 05077237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Method of encapsulating a semiconductor element using a resin mold having upper and lower mold half resin inflow openings' [patent_app_type] => 1 [patent_app_number] => 7/583813 [patent_app_country] => US [patent_app_date] => 1990-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3070 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077237.pdf [firstpage_image] =>[orig_patent_app_number] => 583813 [rel_patent_id] =>[rel_patent_doc_number] =>)