Search

David E. Martinez

Examiner (ID: 12227, Phone: (571)272-4152 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2181, 3634, 2182
Total Applications
982
Issued Applications
835
Pending Applications
33
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17114163 [patent_doc_number] => 20210294760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/011017 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011017
Semiconductor storage device and control method thereof for various interface standards Sep 2, 2020 Issued
Array ( [id] => 17667006 [patent_doc_number] => 11360701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Memory and storage controller with integrated memory coherency interconnect [patent_app_type] => utility [patent_app_number] => 17/010739 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010739
Memory and storage controller with integrated memory coherency interconnect Sep 1, 2020 Issued
Array ( [id] => 17838352 [patent_doc_number] => 20220275657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => GUARDRAIL SAFETY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/637616 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/637616
GUARDRAIL SAFETY SYSTEM AND METHOD Aug 23, 2020 Pending
Array ( [id] => 17432629 [patent_doc_number] => 20220060339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SYSTEM AND METHOD OF UTILIZING A COMPONENT OF AN INFORMATION HANDLING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/999495 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999495
System and method of utilizing a component of an information handling system Aug 20, 2020 Issued
Array ( [id] => 17413827 [patent_doc_number] => 20220048731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SAFETY LOCKOUT ON PATHS TO REGIONS OF HEIGHTENED RISK [patent_app_type] => utility [patent_app_number] => 16/992843 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992843
SAFETY LOCKOUT ON PATHS TO REGIONS OF HEIGHTENED RISK Aug 12, 2020 Pending
Array ( [id] => 16918792 [patent_doc_number] => 20210191884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/983471 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983471
Storage controller managing completion timing, and operating method thereof Aug 2, 2020 Issued
Array ( [id] => 17387673 [patent_doc_number] => 20220035525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => CONTROLLING SSD PERFORMANCE BY THE NUMBER OF ACTIVE MEMORY DIES [patent_app_type] => utility [patent_app_number] => 16/983992 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983992
Controlling SSD performance by the number of active memory dies Aug 2, 2020 Issued
Array ( [id] => 17001129 [patent_doc_number] => 11079939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => Distributing I/O Q-connections of subsytems among hosts [patent_app_type] => utility [patent_app_number] => 16/947397 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947397
Distributing I/O Q-connections of subsytems among hosts Jul 29, 2020 Issued
Array ( [id] => 17309147 [patent_doc_number] => 11210260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Systems and methods for monitoring serial communication between devices [patent_app_type] => utility [patent_app_number] => 16/942417 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3932 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942417
Systems and methods for monitoring serial communication between devices Jul 28, 2020 Issued
Array ( [id] => 17682500 [patent_doc_number] => 11366754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Adjustable buffer memory space [patent_app_type] => utility [patent_app_number] => 16/941177 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13080 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941177
Adjustable buffer memory space Jul 27, 2020 Issued
Array ( [id] => 16423692 [patent_doc_number] => 20200348890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/932426 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932426 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932426
Processing system including one-time programmable memory with original life cycle data, related integrated circuit, device and method Jul 16, 2020 Issued
Array ( [id] => 19197780 [patent_doc_number] => 11995018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Determining a private connection between devices or functions of a serial bus [patent_app_type] => utility [patent_app_number] => 16/931073 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5944 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931073
Determining a private connection between devices or functions of a serial bus Jul 15, 2020 Issued
Array ( [id] => 17238415 [patent_doc_number] => 11182295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Coherence protocol for distributed caches [patent_app_type] => utility [patent_app_number] => 16/916474 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916474
Coherence protocol for distributed caches Jun 29, 2020 Issued
Array ( [id] => 16378240 [patent_doc_number] => 20200327082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => COMPENSATING DC LOSS IN USB 2.0 HIGH SPEED APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/915751 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915751
COMPENSATING DC LOSS IN USB 2.0 HIGH SPEED APPLICATIONS Jun 28, 2020 Abandoned
Array ( [id] => 17636941 [patent_doc_number] => 11347665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory module threading with staggered data transfers [patent_app_type] => utility [patent_app_number] => 16/914221 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914221
Memory module threading with staggered data transfers Jun 25, 2020 Issued
Array ( [id] => 17316649 [patent_doc_number] => 20210405698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => DOCKING STATION AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/911729 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911729 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911729
Docking station and control method capable of automatically setting uplink port Jun 24, 2020 Issued
Array ( [id] => 16364286 [patent_doc_number] => 20200321037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => EFFICIENT CONTROL OF MEMORY CORE CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/905229 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905229 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905229
Efficient control of memory core circuits Jun 17, 2020 Issued
Array ( [id] => 17636946 [patent_doc_number] => 11347670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => System and interface circuit for driving data transmission line to termination voltage [patent_app_type] => utility [patent_app_number] => 16/890462 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4202 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890462
System and interface circuit for driving data transmission line to termination voltage Jun 1, 2020 Issued
Array ( [id] => 16508205 [patent_doc_number] => 20200387461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => PROCESSING CHIP, CHIP SYSTEM AND OPERATION METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/885711 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885711
Processing chip having different modes and corresponding chip system and operation method of the same May 27, 2020 Issued
Array ( [id] => 17121178 [patent_doc_number] => 11132313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Data conversion control apparatus, memory device and memory system [patent_app_type] => utility [patent_app_number] => 16/881016 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5230 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881016 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881016
Data conversion control apparatus, memory device and memory system May 21, 2020 Issued
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