
David E. Martinez
Examiner (ID: 12227, Phone: (571)272-4152 , Office: P/2181 )
| Most Active Art Unit | 2181 |
| Art Unit(s) | 2181, 3634, 2182 |
| Total Applications | 982 |
| Issued Applications | 835 |
| Pending Applications | 33 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17151149
[patent_doc_number] => 11144226
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => Intelligent path selection and load balancing
[patent_app_type] => utility
[patent_app_number] => 16/459166
[patent_app_country] => US
[patent_app_date] => 2019-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 13378
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459166
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/459166 | Intelligent path selection and load balancing | Jun 30, 2019 | Issued |
Array
(
[id] => 16501530
[patent_doc_number] => 10866915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-15
[patent_title] => Method for increasing the compatibility of displayport
[patent_app_type] => utility
[patent_app_number] => 16/457703
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4835
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457703
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/457703 | Method for increasing the compatibility of displayport | Jun 27, 2019 | Issued |
Array
(
[id] => 17824555
[patent_doc_number] => 11429503
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-30
[patent_title] => Auto-detection of interconnect hangs in integrated circuits
[patent_app_type] => utility
[patent_app_number] => 16/456902
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4017
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456902
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/456902 | Auto-detection of interconnect hangs in integrated circuits | Jun 27, 2019 | Issued |
Array
(
[id] => 17061987
[patent_doc_number] => 11106589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Cache control in a parallel processing system
[patent_app_type] => utility
[patent_app_number] => 16/453172
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 8710
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453172
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453172 | Cache control in a parallel processing system | Jun 25, 2019 | Issued |
Array
(
[id] => 15412655
[patent_doc_number] => 20200026650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-23
[patent_title] => ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/452621
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12444
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452621
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/452621 | Arithmetic processing device and arithmetic processing method of controlling prefetch of cache memory | Jun 25, 2019 | Issued |
Array
(
[id] => 16535299
[patent_doc_number] => 10877900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-29
[patent_title] => Enabling faster and regulated device initialization times
[patent_app_type] => utility
[patent_app_number] => 16/453146
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 15034
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453146
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453146 | Enabling faster and regulated device initialization times | Jun 25, 2019 | Issued |
Array
(
[id] => 16544695
[patent_doc_number] => 20200411110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => PREEMPTIVE MITIGATION OF CROSS-TEMPERATURE EFFECTS IN A NON-VOLATILE MEMORY (NVM)
[patent_app_type] => utility
[patent_app_number] => 16/453211
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10169
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453211
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453211 | Preemptive mitigation of cross-temperature effects in a non-volatile memory (NVM) | Jun 25, 2019 | Issued |
Array
(
[id] => 16744981
[patent_doc_number] => 10969969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Use of recovery behavior for prognosticating and in-situ repair of data storage devices
[patent_app_type] => utility
[patent_app_number] => 16/453368
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7054
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453368
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453368 | Use of recovery behavior for prognosticating and in-situ repair of data storage devices | Jun 25, 2019 | Issued |
Array
(
[id] => 16308437
[patent_doc_number] => 10777240
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-15
[patent_title] => Efficient control of memory core circuits
[patent_app_type] => utility
[patent_app_number] => 16/453012
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 22894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453012
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453012 | Efficient control of memory core circuits | Jun 25, 2019 | Issued |
Array
(
[id] => 16667002
[patent_doc_number] => 10936248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Data writing method with verifying a part of data, memory controlling circuit unit and memory storage device
[patent_app_type] => utility
[patent_app_number] => 16/452540
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 9224
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452540
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/452540 | Data writing method with verifying a part of data, memory controlling circuit unit and memory storage device | Jun 25, 2019 | Issued |
Array
(
[id] => 17379918
[patent_doc_number] => 11237934
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-01
[patent_title] => Method for error management in bus communication and bus communication system
[patent_app_type] => utility
[patent_app_number] => 16/450397
[patent_app_country] => US
[patent_app_date] => 2019-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4004
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450397
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/450397 | Method for error management in bus communication and bus communication system | Jun 23, 2019 | Issued |
Array
(
[id] => 16649608
[patent_doc_number] => 10926768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-23
[patent_title] => Vehicle drive and control system
[patent_app_type] => utility
[patent_app_number] => 16/445089
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 32
[patent_no_of_words] => 21509
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 360
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445089
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445089 | Vehicle drive and control system | Jun 17, 2019 | Issued |
Array
(
[id] => 16641637
[patent_doc_number] => 10919463
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-16
[patent_title] => Vehicle drive and control system
[patent_app_type] => utility
[patent_app_number] => 16/445109
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 32
[patent_no_of_words] => 21512
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445109
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445109 | Vehicle drive and control system | Jun 17, 2019 | Issued |
Array
(
[id] => 16486336
[patent_doc_number] => 20200379942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => SYNCHRONIZATION OF AUDIO ACROSS MULTIPLE DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/428088
[patent_app_country] => US
[patent_app_date] => 2019-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9141
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428088
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/428088 | Synchronization of audio across multiple devices | May 30, 2019 | Issued |
Array
(
[id] => 16927069
[patent_doc_number] => 11048552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => High-speed broadside communications and control system
[patent_app_type] => utility
[patent_app_number] => 16/425606
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 15342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425606
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/425606 | High-speed broadside communications and control system | May 28, 2019 | Issued |
Array
(
[id] => 16745084
[patent_doc_number] => 10970074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Broadside random access memory for low cycle memory access and additional functions
[patent_app_type] => utility
[patent_app_number] => 16/424913
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 14145
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424913
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424913 | Broadside random access memory for low cycle memory access and additional functions | May 28, 2019 | Issued |
Array
(
[id] => 15182461
[patent_doc_number] => 20190361822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => A METHOD FOR SENDING DATA, CORRESPONDING COMPUTER PROGRAM AND SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/418192
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4003
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418192
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/418192 | Method for sending by an upstream device to a downstream device data from a virtual channel sharing a same input buffer memory of the downstream device, corresponding computer program and system | May 20, 2019 | Issued |
Array
(
[id] => 16018041
[patent_doc_number] => 20200183864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-11
[patent_title] => PERIPHERAL DEVICE WITH EMBEDDED VIDEO CODEC FUNCTIONALITY
[patent_app_type] => utility
[patent_app_number] => 16/415759
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5892
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415759
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/415759 | Peripheral device with embedded video codec functionality | May 16, 2019 | Issued |
Array
(
[id] => 16636975
[patent_doc_number] => 10915485
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Circuit for asynchronous data transfer
[patent_app_type] => utility
[patent_app_number] => 16/414793
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7945
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414793
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/414793 | Circuit for asynchronous data transfer | May 16, 2019 | Issued |
Array
(
[id] => 14811273
[patent_doc_number] => 20190272246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-05
[patent_title] => EXPANSION CARD CONFIGURATION OF MOTHERBOARD
[patent_app_type] => utility
[patent_app_number] => 16/414394
[patent_app_country] => US
[patent_app_date] => 2019-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414394
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/414394 | Expansion card configuration of motherboard | May 15, 2019 | Issued |