David E. Martinez

Array ( [id] => 15328191 [patent_doc_number] => 20200004425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => STORAGE SYSTEM, COPY CONTROL METHOD, AND COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 16/484607 [patent_app_country] => US [patent_app_date] => 2017-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13075957 [patent_doc_number] => 10058031 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Lawn tractor with electronic drive and control system [patent_app_type] => utility [patent_app_number] => 15/640300 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 17867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14982743 [patent_doc_number] => 10445285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Integrated data concentrator for multi-sensor MEMS systems [patent_app_type] => utility [patent_app_number] => 15/639543 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15639543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13226575 [patent_doc_number] => 10127063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Devices and systems with virtual devices that may be selectively enabled [patent_app_type] => utility [patent_app_number] => 15/635174 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 9802 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12691990 [patent_doc_number] => 20180122496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING A PLURALITY OF INPUT/OUTPUT UNITS AND AN OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/632962 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11982202 [patent_doc_number] => 20170286355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) HOSTS ADAPTED TO SUPPORT REMOTE PCIe ENDPOINTS' [patent_app_type] => utility [patent_app_number] => 15/631927 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6202 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14766701 [patent_doc_number] => 10394747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Implementing hierarchical PCI express switch topology over coherent mesh interconnect [patent_app_type] => utility [patent_app_number] => 15/609433 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13583873 [patent_doc_number] => 20180343485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => Environment Identification Based on Multiple Proximate Hubs [patent_app_type] => utility [patent_app_number] => 15/607610 [patent_app_country] => US [patent_app_date] => 2017-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11958249 [patent_doc_number] => 20170262401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS' [patent_app_type] => utility [patent_app_number] => 15/607362 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14013 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11958250 [patent_doc_number] => 20170262402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS' [patent_app_type] => utility [patent_app_number] => 15/607367 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14015 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11958251 [patent_doc_number] => 20170262403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS' [patent_app_type] => utility [patent_app_number] => 15/607371 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14015 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12986434 [patent_doc_number] => 20170344507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => METHOD FOR MANAGING DOCKING DEVICE AND DOCKING DEVICE [patent_app_type] => utility [patent_app_number] => 15/605203 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14427101 [patent_doc_number] => 10318354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Methods and apparatus for command list processing in performing parallel IO operations [patent_app_type] => utility [patent_app_number] => 15/601319 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10615 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13860245 [patent_doc_number] => 10191842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/489282 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11759230 [patent_doc_number] => 20170206099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'CIRCUITRY FOR CONFIGURING ENTITIES' [patent_app_type] => utility [patent_app_number] => 15/478944 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5026 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13466585 [patent_doc_number] => 20180284835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SEPARATE CLOCK SYNCHRONOUS ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/475328 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13471393 [patent_doc_number] => 20180287239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SINGLE WIRE COMMUNICATION BOARD-TO-BOARD INTERCONNECT [patent_app_type] => utility [patent_app_number] => 15/473330 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15953007 [patent_doc_number] => 10664411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Chained bus memory device [patent_app_type] => utility [patent_app_number] => 15/470590 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13417623 [patent_doc_number] => 20180260354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SYSTEM AND METHOD FOR FLEXIBLE CONNECTION OF REDUNDANT INPUT-OUTPUT MODULES OR OTHER DEVICES [patent_app_type] => utility [patent_app_number] => 15/452433 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11989428 [patent_doc_number] => 20170293583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/448910 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13673 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448910 [rel_patent_id] =>[rel_patent_doc_number] =>)