David E. Martinez

Array ( [id] => 12256051 [patent_doc_number] => 09928195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Interconnect and method of operation of an interconnect for ordered write observation (OWO)' [patent_app_type] => utility [patent_app_number] => 14/959170 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12414372 [patent_doc_number] => 09971733 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-15 [patent_title] => Scalable 2.5D interface circuitry [patent_app_type] => utility [patent_app_number] => 14/960175 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10816265 [patent_doc_number] => 20160162426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'OPTIMAL SAMPLING OF DATA-BUS SIGNALS USING CONFIGURABLE INDIVIDUAL TIME DELAYS' [patent_app_type] => utility [patent_app_number] => 14/957617 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14957617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11086149 [patent_doc_number] => 20160283114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/956455 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15335 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11664966 [patent_doc_number] => 20170153684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'INTERCONNECT SERIALIZATION SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/955998 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13110307 [patent_doc_number] => 10073807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Logic-based decoder for crosstalk-harnessed signaling [patent_app_type] => utility [patent_app_number] => 14/955043 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5346 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11078074 [patent_doc_number] => 20160275038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'METHOD FOR COMMUNICATION USING PCI EXPRESS DEDICATED COMMUNICATION MODULE AND NETWORK DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/954192 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3559 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11664941 [patent_doc_number] => 20170153660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'AUTOMATIC CLOCK CONFIGURATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/953975 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4014 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13512195 [patent_doc_number] => 20180307640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => DATA TRANSFER APPARATUS, DATA TRANSFER METHOD, AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 15/765454 [patent_app_country] => US [patent_app_date] => 2015-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12514341 [patent_doc_number] => 10002246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Hardware isolated secure processing system within a secure element [patent_app_type] => utility [patent_app_number] => 14/949306 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7925 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10653476 [patent_doc_number] => 09369753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Methods, systems, and media for controlling a bi-directional HDMI port' [patent_app_type] => utility [patent_app_number] => 14/935050 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8043 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11501666 [patent_doc_number] => 20170075851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'MULTIFUNCTION EXPANSION MODULE' [patent_app_type] => utility [patent_app_number] => 14/855770 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1379 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14855770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14330919 [patent_doc_number] => 10296478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Expansion card configuration of motherboard [patent_app_type] => utility [patent_app_number] => 14/852126 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4140 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027097 [patent_doc_number] => 20160224053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'TIMER-BASED PROCESSING UNIT OPERATIONAL SCALING EMPLOYING TIMER RESETTING ON IDLE PROCESS SCHEDULING' [patent_app_type] => utility [patent_app_number] => 14/851155 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8531 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10731845 [patent_doc_number] => 20160077995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'VARIABLE FRAME LENGTH VIRTUAL GPIO WITH A MODIFIED UART INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/850809 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8069 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11494440 [patent_doc_number] => 20170068626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) PSEUDO-VIRTUAL CHANNELS USING VENDOR DEFINED MESSAGES' [patent_app_type] => utility [patent_app_number] => 14/848929 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4815 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746243 [patent_doc_number] => 20160092394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INFORMATION PROCESSING APPARATUS, CONTROLLING METHOD FOR INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/847473 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3523 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11494448 [patent_doc_number] => 20170068634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'ASYNCHRONOUS MAPPING OF HOT-PLUGGED DEVICE ASSOCIATED WITH VIRTUAL MACHINE' [patent_app_type] => utility [patent_app_number] => 14/844995 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11474012 [patent_doc_number] => 20170060795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SYSTEM AND METHODS TO SUPPORT VENDOR DEFINED USB REQUESTS FOR APPLICATION MANAGED USB DEVICES IN VDI ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/834264 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10470663 [patent_doc_number] => 20150355679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'PORTABLE DEVICE AND PERIPHERAL EXTENSION DOCK' [patent_app_type] => utility [patent_app_number] => 14/827362 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4464 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827362 [rel_patent_id] =>[rel_patent_doc_number] =>)