Search

David G. Muller

Examiner (ID: 18937, Phone: (571)272-4721 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2914, 2974
Total Applications
3653
Issued Applications
3583
Pending Applications
13
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10624570 [patent_doc_number] => 09343520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Organic light-emitting diode display and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/586399 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4329 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14586399 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/586399
Organic light-emitting diode display and method of fabricating the same Dec 29, 2014 Issued
Array ( [id] => 11207933 [patent_doc_number] => 09437565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Semiconductor substrate and semiconductor package structure having the same' [patent_app_type] => utility [patent_app_number] => 14/586735 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14586735 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/586735
Semiconductor substrate and semiconductor package structure having the same Dec 29, 2014 Issued
Array ( [id] => 10993167 [patent_doc_number] => 20160190113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'PASSIVE COMPONENTS IN VIAS IN A STACKED INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/583015 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583015 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583015
Passive components in vias in a stacked integrated circuit package Dec 23, 2014 Issued
Array ( [id] => 10252316 [patent_doc_number] => 20150137312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/580539 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4520 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580539 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580539
Metal fuse structure for improved programming capability Dec 22, 2014 Issued
Array ( [id] => 10984289 [patent_doc_number] => 20160181233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/580900 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11299 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580900
METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS Dec 22, 2014 Abandoned
Array ( [id] => 10376898 [patent_doc_number] => 20150261905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHODS OF PREPARING LAYOUTS FOR SEMICONDUCTOR DEVICES, PHOTOMASKS FORMED USING THE LAYOUTS, AND SEMICONDUCTOR DEVICES FABRICATED USING THE PHOTOMASKS' [patent_app_type] => utility [patent_app_number] => 14/576695 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576695
Methods of preparing layouts for semiconductor devices, photomasks formed using the layouts, and semiconductor devices fabricated using the photomasks Dec 18, 2014 Issued
Array ( [id] => 10537619 [patent_doc_number] => 09263254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Method for making epitaxial structure' [patent_app_type] => utility [patent_app_number] => 14/565436 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7834 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565436
Method for making epitaxial structure Dec 9, 2014 Issued
Array ( [id] => 10395047 [patent_doc_number] => 20150280054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD FOR MAKING LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 14/565430 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565430
Method for making light emitting diode Dec 9, 2014 Issued
Array ( [id] => 10509772 [patent_doc_number] => 09237651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Padless via' [patent_app_type] => utility [patent_app_number] => 14/565383 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3854 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565383 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565383
Padless via Dec 8, 2014 Issued
Array ( [id] => 11391644 [patent_doc_number] => 09552894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Impedance calibration circuit, and semiconductor memory and memory system using the same' [patent_app_type] => utility [patent_app_number] => 14/564404 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564404
Impedance calibration circuit, and semiconductor memory and memory system using the same Dec 8, 2014 Issued
Array ( [id] => 11925664 [patent_doc_number] => 09793254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'TVS structures for high surge and low capacitance' [patent_app_type] => utility [patent_app_number] => 14/565392 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 5286 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565392 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565392
TVS structures for high surge and low capacitance Dec 8, 2014 Issued
Array ( [id] => 10202102 [patent_doc_number] => 20150087090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'MONITOR TEST KEY OF EPI PROFILE' [patent_app_type] => utility [patent_app_number] => 14/555314 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555314 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555314
Monitor test key of epi profile Nov 25, 2014 Issued
Array ( [id] => 10394803 [patent_doc_number] => 20150279810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'WIRE BONDING METHOD EMPLOYING TWO SCRUB SETTINGS' [patent_app_type] => utility [patent_app_number] => 14/552472 [patent_app_country] => US [patent_app_date] => 2014-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14552472 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/552472
Wire bonding method employing two scrub settings Nov 23, 2014 Issued
Array ( [id] => 10802685 [patent_doc_number] => 20160148842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'DICING OF LOW-K WAFERS' [patent_app_type] => utility [patent_app_number] => 14/552086 [patent_app_country] => US [patent_app_date] => 2014-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14552086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/552086
DICING OF LOW-K WAFERS Nov 23, 2014 Abandoned
Array ( [id] => 12554430 [patent_doc_number] => 10014368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/102577 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102577
Semiconductor device and manufacturing method of semiconductor device Nov 18, 2014 Issued
Array ( [id] => 12554430 [patent_doc_number] => 10014368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/102577 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102577
Semiconductor device and manufacturing method of semiconductor device Nov 18, 2014 Issued
Array ( [id] => 12554430 [patent_doc_number] => 10014368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/102577 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102577
Semiconductor device and manufacturing method of semiconductor device Nov 18, 2014 Issued
Array ( [id] => 12554430 [patent_doc_number] => 10014368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/102577 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102577
Semiconductor device and manufacturing method of semiconductor device Nov 18, 2014 Issued
Array ( [id] => 10244036 [patent_doc_number] => 20150129031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'METAL FOIL METALLIZATION FOR BACKPLANE-ATTACHED SOLAR CELLS AND MODULES' [patent_app_type] => utility [patent_app_number] => 14/539978 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11405 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539978 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539978
Metal foil metallization for backplane-attached solar cells and modules Nov 11, 2014 Issued
Array ( [id] => 10249260 [patent_doc_number] => 20150134257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Automatic Wellbore Condition Indicator and Manager' [patent_app_type] => utility [patent_app_number] => 14/538672 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8980 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538672 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538672
Automatic wellbore condition indicator and manager Nov 10, 2014 Issued
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