Search

David H. Kruse

Examiner (ID: 8531, Phone: (571)272-0799 , Office: P/1663 )

Most Active Art Unit
1663
Art Unit(s)
1638, 1663
Total Applications
2064
Issued Applications
1533
Pending Applications
160
Abandoned Applications
397

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8070633 [patent_doc_number] => 20110241708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'APPARATUS FOR PREDETERMINED COMPONENT PLACEMENT TO A TARGET PLATFORM' [patent_app_type] => utility [patent_app_number] => 13/157543 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12881 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241708.pdf [firstpage_image] =>[orig_patent_app_number] => 13157543 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/157543
APPARATUS FOR PREDETERMINED COMPONENT PLACEMENT TO A TARGET PLATFORM Jun 9, 2011 Abandoned
Array ( [id] => 8435984 [patent_doc_number] => 08283755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Multichip semiconductor device, chip therefor and method of formation thereof' [patent_app_type] => utility [patent_app_number] => 13/067180 [patent_app_country] => US [patent_app_date] => 2011-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 76 [patent_no_of_words] => 16390 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067180 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067180
Multichip semiconductor device, chip therefor and method of formation thereof May 12, 2011 Issued
Array ( [id] => 5932414 [patent_doc_number] => 20110210395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'TRANSISTORS WITH IMMERSED CONTACTS' [patent_app_type] => utility [patent_app_number] => 13/105484 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210395.pdf [firstpage_image] =>[orig_patent_app_number] => 13105484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105484
Transistors with immersed contacts May 10, 2011 Issued
Array ( [id] => 7698901 [patent_doc_number] => 20110227689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'Method of Creating Spiral Inductor having High Q Value' [patent_app_type] => utility [patent_app_number] => 13/102531 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2268 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227689.pdf [firstpage_image] =>[orig_patent_app_number] => 13102531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102531
Method of creating spiral inductor having high Q value May 5, 2011 Issued
Array ( [id] => 9324104 [patent_doc_number] => 08659130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Power module and power module manufacturing method' [patent_app_type] => utility [patent_app_number] => 13/640512 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 21967 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13640512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/640512
Power module and power module manufacturing method Apr 25, 2011 Issued
Array ( [id] => 8920872 [patent_doc_number] => 08486805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Through-silicon via and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/142757 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3937 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142757 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/142757
Through-silicon via and method for forming the same Apr 10, 2011 Issued
Array ( [id] => 8426746 [patent_doc_number] => 20120248621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS' [patent_app_type] => utility [patent_app_number] => 13/077292 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10833 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/077292
METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS Mar 30, 2011 Abandoned
Array ( [id] => 6047770 [patent_doc_number] => 20110207300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 13/072593 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10628 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20110207300.pdf [firstpage_image] =>[orig_patent_app_number] => 13072593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/072593
ELECTRONIC DEVICES Mar 24, 2011 Abandoned
Array ( [id] => 9691645 [patent_doc_number] => 08822238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Apparatus and method for predetermined component placement to a target platform' [patent_app_type] => utility [patent_app_number] => 13/049302 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 12853 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13049302 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/049302
Apparatus and method for predetermined component placement to a target platform Mar 15, 2011 Issued
Array ( [id] => 6153090 [patent_doc_number] => 20110156001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'NITRIDE-BASED LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/046490 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4411 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156001.pdf [firstpage_image] =>[orig_patent_app_number] => 13046490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/046490
Nitride-based light-emitting device Mar 10, 2011 Issued
Array ( [id] => 6015838 [patent_doc_number] => 20110223699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Wiring Material, Semiconductor Device Provided with a Wiring Using the Wiring Material and Method of Manufacturing Thereof' [patent_app_type] => utility [patent_app_number] => 13/042751 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14097 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20110223699.pdf [firstpage_image] =>[orig_patent_app_number] => 13042751 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042751
Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof Mar 7, 2011 Issued
Array ( [id] => 8680900 [patent_doc_number] => 20130049184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'ELECTRIC DEVICE AND PRODUCTION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/583044 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9006 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13583044 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/583044
ELECTRIC DEVICE AND PRODUCTION METHOD THEREFOR Mar 3, 2011 Abandoned
Array ( [id] => 10876111 [patent_doc_number] => 08900896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Implantation before epitaxial growth for photonic integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/030094 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5760 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13030094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/030094
Implantation before epitaxial growth for photonic integrated circuits Feb 16, 2011 Issued
Array ( [id] => 6143700 [patent_doc_number] => 20110130005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/024711 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3563 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20110130005.pdf [firstpage_image] =>[orig_patent_app_number] => 13024711 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024711
Processing for overcoming extreme topography Feb 9, 2011 Issued
Array ( [id] => 6212999 [patent_doc_number] => 20110136299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/016453 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2073 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20110136299.pdf [firstpage_image] =>[orig_patent_app_number] => 13016453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016453
Leadframe for leadless package, structure and manufacturing method using the same Jan 27, 2011 Issued
Array ( [id] => 6208404 [patent_doc_number] => 20110133322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/016341 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2073 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133322.pdf [firstpage_image] =>[orig_patent_app_number] => 13016341 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016341
Leadframe for leadless package, structure and manufacturing method using the same Jan 27, 2011 Issued
Array ( [id] => 8166463 [patent_doc_number] => 20120104609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DISCRETE CIRCUIT COMPONENT HAVING COPPER BLOCK ELECTRODES AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/985547 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2773 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104609.pdf [firstpage_image] =>[orig_patent_app_number] => 12985547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985547
DISCRETE CIRCUIT COMPONENT HAVING COPPER BLOCK ELECTRODES AND METHOD OF FABRICATION Jan 5, 2011 Abandoned
Array ( [id] => 6189125 [patent_doc_number] => 20110171812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/984895 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7932 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171812.pdf [firstpage_image] =>[orig_patent_app_number] => 12984895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984895
Fabrication of substrates with a useful layer of monocrystalline semiconductor material Jan 4, 2011 Issued
Array ( [id] => 6058991 [patent_doc_number] => 20110198762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'PANELIZED PACKAGING WITH TRANSFERRED DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 12/985212 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198762.pdf [firstpage_image] =>[orig_patent_app_number] => 12985212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985212
PANELIZED PACKAGING WITH TRANSFERRED DIELECTRIC Jan 4, 2011 Abandoned
Array ( [id] => 5940902 [patent_doc_number] => 20110101522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Multichip semiconductor device, chip therefor and method of formation thereof' [patent_app_type] => utility [patent_app_number] => 12/926104 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16262 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20110101522.pdf [firstpage_image] =>[orig_patent_app_number] => 12926104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926104
Multichip semiconductor device, chip therefor and method of formation thereof Oct 25, 2010 Issued
Menu