
David H. Kruse
Examiner (ID: 5674, Phone: (571)272-0799 , Office: P/1663 )
| Most Active Art Unit | 1663 |
| Art Unit(s) | 1638, 1663 |
| Total Applications | 2040 |
| Issued Applications | 1524 |
| Pending Applications | 150 |
| Abandoned Applications | 393 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1419473
[patent_doc_number] => 06512183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-28
[patent_title] => 'Electronic component mounted member and repair method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/893106
[patent_app_country] => US
[patent_app_date] => 2001-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4424
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/512/06512183.pdf
[firstpage_image] =>[orig_patent_app_number] => 09893106
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/893106 | Electronic component mounted member and repair method thereof | Jun 26, 2001 | Issued |
Array
(
[id] => 1455036
[patent_doc_number] => 06462281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-08
[patent_title] => 'High-insulated stud and printed circuit board therewith'
[patent_app_type] => B2
[patent_app_number] => 09/891803
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 3585
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/462/06462281.pdf
[firstpage_image] =>[orig_patent_app_number] => 09891803
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/891803 | High-insulated stud and printed circuit board therewith | Jun 25, 2001 | Issued |
Array
(
[id] => 6631628
[patent_doc_number] => 20030006061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'HYBRID SURFACE MOUNT AND PIN THRU HOLE CIRCUIT BOARD'
[patent_app_type] => new
[patent_app_number] => 09/885614
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5229
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20030006061.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885614
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885614 | Hybrid surface mount and pin thru hole circuit board | Jun 19, 2001 | Issued |
Array
(
[id] => 6517456
[patent_doc_number] => 20020108776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-15
[patent_title] => 'Multilayer printed circuit board and method of making the same'
[patent_app_type] => new
[patent_app_number] => 09/880037
[patent_app_country] => US
[patent_app_date] => 2001-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5393
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20020108776.pdf
[firstpage_image] =>[orig_patent_app_number] => 09880037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/880037 | Multilayer printed circuit board and method of making the same | Jun 13, 2001 | Issued |
Array
(
[id] => 6137701
[patent_doc_number] => 20020000571
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'High-temperature superconductor arrangement'
[patent_app_type] => new
[patent_app_number] => 09/867426
[patent_app_country] => US
[patent_app_date] => 2001-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2774
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000571.pdf
[firstpage_image] =>[orig_patent_app_number] => 09867426
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/867426 | High-temperature superconductor arrangement | May 30, 2001 | Abandoned |
Array
(
[id] => 1427269
[patent_doc_number] => 06504111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-07
[patent_title] => 'Solid via layer to layer interconnect'
[patent_app_type] => B2
[patent_app_number] => 09/867312
[patent_app_country] => US
[patent_app_date] => 2001-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2133
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/504/06504111.pdf
[firstpage_image] =>[orig_patent_app_number] => 09867312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/867312 | Solid via layer to layer interconnect | May 28, 2001 | Issued |
Array
(
[id] => 6894933
[patent_doc_number] => 20010025723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-04
[patent_title] => 'Mounting structure of electronic component on substrate board'
[patent_app_type] => new
[patent_app_number] => 09/858500
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6749
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20010025723.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858500
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858500 | Mounting structure of electronic component on substrate board | May 16, 2001 | Issued |
Array
(
[id] => 1538356
[patent_doc_number] => 06337796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-01-08
[patent_title] => 'Semiconductor device mount structure having heat dissipating member for dissipating heat generated from semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/852701
[patent_app_country] => US
[patent_app_date] => 2001-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3591
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/337/06337796.pdf
[firstpage_image] =>[orig_patent_app_number] => 09852701
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/852701 | Semiconductor device mount structure having heat dissipating member for dissipating heat generated from semiconductor device | May 10, 2001 | Issued |
Array
(
[id] => 5782005
[patent_doc_number] => 20020157861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Printed circuit board with mixed metallurgy pads and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 09/844814
[patent_app_country] => US
[patent_app_date] => 2001-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3416
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20020157861.pdf
[firstpage_image] =>[orig_patent_app_number] => 09844814
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/844814 | Printed circuit board with mixed metallurgy pads and method of fabrication | Apr 26, 2001 | Issued |
Array
(
[id] => 6224794
[patent_doc_number] => 20020004324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin'
[patent_app_type] => new
[patent_app_number] => 09/829441
[patent_app_country] => US
[patent_app_date] => 2001-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14135
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20020004324.pdf
[firstpage_image] =>[orig_patent_app_number] => 09829441
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/829441 | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions | Apr 9, 2001 | Issued |
Array
(
[id] => 6152966
[patent_doc_number] => 20020144840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Leadframe package with dummy chip'
[patent_app_type] => new
[patent_app_number] => 09/829506
[patent_app_country] => US
[patent_app_date] => 2001-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1153
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20020144840.pdf
[firstpage_image] =>[orig_patent_app_number] => 09829506
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/829506 | Leadframe package with dummy chip | Apr 8, 2001 | Abandoned |
Array
(
[id] => 996754
[patent_doc_number] => 06914196
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Reel-deployed printed circuit board'
[patent_app_type] => utility
[patent_app_number] => 09/827112
[patent_app_country] => US
[patent_app_date] => 2001-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 3646
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/914/06914196.pdf
[firstpage_image] =>[orig_patent_app_number] => 09827112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/827112 | Reel-deployed printed circuit board | Apr 4, 2001 | Issued |
Array
(
[id] => 1266025
[patent_doc_number] => 06660942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-09
[patent_title] => 'Semiconductor device with an exposed external-connection terminal'
[patent_app_type] => B2
[patent_app_number] => 09/826512
[patent_app_country] => US
[patent_app_date] => 2001-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 10410
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/660/06660942.pdf
[firstpage_image] =>[orig_patent_app_number] => 09826512
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/826512 | Semiconductor device with an exposed external-connection terminal | Apr 4, 2001 | Issued |
Array
(
[id] => 1213781
[patent_doc_number] => 06710255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Printed circuit board having buried intersignal capacitance and method of making'
[patent_app_type] => B2
[patent_app_number] => 09/822715
[patent_app_country] => US
[patent_app_date] => 2001-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2639
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/710/06710255.pdf
[firstpage_image] =>[orig_patent_app_number] => 09822715
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/822715 | Printed circuit board having buried intersignal capacitance and method of making | Mar 29, 2001 | Issued |
Array
(
[id] => 1501962
[patent_doc_number] => 06486411
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'Semiconductor module having solder bumps and solder portions with different materials and compositions and circuit substrate'
[patent_app_type] => B2
[patent_app_number] => 09/811445
[patent_app_country] => US
[patent_app_date] => 2001-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 6197
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486411.pdf
[firstpage_image] =>[orig_patent_app_number] => 09811445
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/811445 | Semiconductor module having solder bumps and solder portions with different materials and compositions and circuit substrate | Mar 19, 2001 | Issued |
Array
(
[id] => 6027934
[patent_doc_number] => 20020017399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-14
[patent_title] => 'Coaxial via hole and process of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 09/809310
[patent_app_country] => US
[patent_app_date] => 2001-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5349
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20020017399.pdf
[firstpage_image] =>[orig_patent_app_number] => 09809310
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/809310 | Coaxial via hole and process of fabricating the same | Mar 15, 2001 | Issued |
Array
(
[id] => 1572451
[patent_doc_number] => 06468091
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-22
[patent_title] => 'Electrical distribution center'
[patent_app_type] => B2
[patent_app_number] => 09/802436
[patent_app_country] => US
[patent_app_date] => 2001-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1760
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/468/06468091.pdf
[firstpage_image] =>[orig_patent_app_number] => 09802436
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802436 | Electrical distribution center | Mar 8, 2001 | Issued |
Array
(
[id] => 6986234
[patent_doc_number] => 20010036066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Method and apparatus for delivering power to high performance electronic assemblies'
[patent_app_type] => new
[patent_app_number] => 09/801437
[patent_app_country] => US
[patent_app_date] => 2001-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7682
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20010036066.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801437
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801437 | Apparatus for delivering power to high performance electronic assemblies | Mar 7, 2001 | Issued |
Array
(
[id] => 4308307
[patent_doc_number] => 06326557
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Multi-layer circuit board'
[patent_app_type] => 1
[patent_app_number] => 9/799900
[patent_app_country] => US
[patent_app_date] => 2001-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2583
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/326/06326557.pdf
[firstpage_image] =>[orig_patent_app_number] => 799900
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799900 | Multi-layer circuit board | Mar 5, 2001 | Issued |
Array
(
[id] => 1491580
[patent_doc_number] => 06417460
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Multi-layer circuit board having signal, ground and power layers'
[patent_app_type] => B1
[patent_app_number] => 09/800412
[patent_app_country] => US
[patent_app_date] => 2001-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3987
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417460.pdf
[firstpage_image] =>[orig_patent_app_number] => 09800412
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800412 | Multi-layer circuit board having signal, ground and power layers | Mar 5, 2001 | Issued |