| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1590390
[patent_doc_number] => 06483045
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Via plug layout structure for connecting different metallic layers'
[patent_app_type] => B1
[patent_app_number] => 09/626409
[patent_app_country] => US
[patent_app_date] => 2000-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2564
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/483/06483045.pdf
[firstpage_image] =>[orig_patent_app_number] => 09626409
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/626409 | Via plug layout structure for connecting different metallic layers | Jul 25, 2000 | Issued |
Array
(
[id] => 7634484
[patent_doc_number] => 06657136
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Termination board for mounting on circuit board'
[patent_app_type] => B1
[patent_app_number] => 09/608528
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3438
[patent_no_of_claims] => 13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/657/06657136.pdf
[firstpage_image] =>[orig_patent_app_number] => 09608528
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/608528 | Termination board for mounting on circuit board | Jun 29, 2000 | Issued |
Array
(
[id] => 1393759
[patent_doc_number] => 06548767
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Multi-layer printed circuit board having via holes formed from both sides thereof'
[patent_app_type] => B1
[patent_app_number] => 09/604902
[patent_app_country] => US
[patent_app_date] => 2000-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 3918
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 192
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548767.pdf
[firstpage_image] =>[orig_patent_app_number] => 09604902
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/604902 | Multi-layer printed circuit board having via holes formed from both sides thereof | Jun 27, 2000 | Issued |
Array
(
[id] => 1441802
[patent_doc_number] => 06335494
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Multiple power distribution for delta-I noise reduction'
[patent_app_type] => B1
[patent_app_number] => 09/602911
[patent_app_country] => US
[patent_app_date] => 2000-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2965
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/335/06335494.pdf
[firstpage_image] =>[orig_patent_app_number] => 09602911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/602911 | Multiple power distribution for delta-I noise reduction | Jun 22, 2000 | Issued |
Array
(
[id] => 1197539
[patent_doc_number] => 06727435
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'Backplane power distribution system'
[patent_app_type] => B1
[patent_app_number] => 09/590564
[patent_app_country] => US
[patent_app_date] => 2000-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2481
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/727/06727435.pdf
[firstpage_image] =>[orig_patent_app_number] => 09590564
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590564 | Backplane power distribution system | Jun 7, 2000 | Issued |
Array
(
[id] => 1509503
[patent_doc_number] => 06441485
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Apparatus for electrically mounting an electronic device to a substrate without soldering'
[patent_app_type] => B1
[patent_app_number] => 09/569716
[patent_app_country] => US
[patent_app_date] => 2000-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2625
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/441/06441485.pdf
[firstpage_image] =>[orig_patent_app_number] => 09569716
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/569716 | Apparatus for electrically mounting an electronic device to a substrate without soldering | May 10, 2000 | Issued |
| 09/463888 | HIGH TEMPERATURE SUPERCONDUCTOR AND METHOD OF MAKING AND USING SAME | Apr 16, 2000 | Abandoned |
Array
(
[id] => 1451800
[patent_doc_number] => 06455786
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Wiring board and manufacturing method thereof and semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/539117
[patent_app_country] => US
[patent_app_date] => 2000-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 28
[patent_no_of_words] => 6442
[patent_no_of_claims] => 12
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[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455786.pdf
[firstpage_image] =>[orig_patent_app_number] => 09539117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/539117 | Wiring board and manufacturing method thereof and semiconductor device | Mar 29, 2000 | Issued |
Array
(
[id] => 4349813
[patent_doc_number] => 06284985
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Ceramic circuit board with a metal plate projected to prevent solder-flow'
[patent_app_type] => 1
[patent_app_number] => 9/534319
[patent_app_country] => US
[patent_app_date] => 2000-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 7270
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284985.pdf
[firstpage_image] =>[orig_patent_app_number] => 534319
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/534319 | Ceramic circuit board with a metal plate projected to prevent solder-flow | Mar 23, 2000 | Issued |
Array
(
[id] => 4308265
[patent_doc_number] => 06326554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Surface mount flexible interconnect and component carrier'
[patent_app_type] => 1
[patent_app_number] => 9/533702
[patent_app_country] => US
[patent_app_date] => 2000-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2010
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[pdf_file] => patents/06/326/06326554.pdf
[firstpage_image] =>[orig_patent_app_number] => 533702
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/533702 | Surface mount flexible interconnect and component carrier | Mar 22, 2000 | Issued |
Array
(
[id] => 1423281
[patent_doc_number] => 06506982
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-14
[patent_title] => 'Multi-layer wiring substrate and manufacturing method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/501596
[patent_app_country] => US
[patent_app_date] => 2000-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/506/06506982.pdf
[firstpage_image] =>[orig_patent_app_number] => 09501596
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/501596 | Multi-layer wiring substrate and manufacturing method thereof | Feb 9, 2000 | Issued |
Array
(
[id] => 5916944
[patent_doc_number] => 20020112885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'Printed circuit board and method for manufacturing same'
[patent_app_type] => new
[patent_app_number] => 09/501296
[patent_app_country] => US
[patent_app_date] => 2000-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2896
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20020112885.pdf
[firstpage_image] =>[orig_patent_app_number] => 09501296
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/501296 | Printed circuit board and method for manufacturing same | Feb 8, 2000 | Issued |
| 09/463312 | PROCESS FOR MANUFACTURING AN ELECTRIC CONDUCTOR WITH SUPERCONDUCTING CORES, AND THUS MANUFACTURED CONDUCTOR | Jan 23, 2000 | Abandoned |
Array
(
[id] => 6106333
[patent_doc_number] => 20020170746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'ORGANIC PACKAGES WITH SOLDERS FOR RELIABLE FLIP CHIP CONNECTIONS'
[patent_app_type] => new
[patent_app_number] => 09/482102
[patent_app_country] => US
[patent_app_date] => 2000-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0170/20020170746.pdf
[firstpage_image] =>[orig_patent_app_number] => 09482102
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/482102 | ORGANIC PACKAGES WITH SOLDERS FOR RELIABLE FLIP CHIP CONNECTIONS | Jan 12, 2000 | Abandoned |
Array
(
[id] => 1420981
[patent_doc_number] => 06518509
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Copper plated invar with acid preclean'
[patent_app_type] => B1
[patent_app_number] => 09/471680
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/518/06518509.pdf
[firstpage_image] =>[orig_patent_app_number] => 09471680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/471680 | Copper plated invar with acid preclean | Dec 22, 1999 | Issued |
Array
(
[id] => 1382493
[patent_doc_number] => 06559390
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Solder connect assembly and method of connecting a semiconductor package and a printed wiring board'
[patent_app_type] => B1
[patent_app_number] => 09/469251
[patent_app_country] => US
[patent_app_date] => 1999-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/559/06559390.pdf
[firstpage_image] =>[orig_patent_app_number] => 09469251
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/469251 | Solder connect assembly and method of connecting a semiconductor package and a printed wiring board | Dec 21, 1999 | Issued |
Array
(
[id] => 1562838
[patent_doc_number] => 06362438
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Enhanced plated-through hole and via contact design'
[patent_app_type] => B1
[patent_app_number] => 09/461901
[patent_app_country] => US
[patent_app_date] => 1999-12-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/362/06362438.pdf
[firstpage_image] =>[orig_patent_app_number] => 09461901
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/461901 | Enhanced plated-through hole and via contact design | Dec 14, 1999 | Issued |
Array
(
[id] => 1515885
[patent_doc_number] => 06420662
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-16
[patent_title] => 'Wiring board'
[patent_app_type] => B1
[patent_app_number] => 09/460244
[patent_app_country] => US
[patent_app_date] => 1999-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/420/06420662.pdf
[firstpage_image] =>[orig_patent_app_number] => 09460244
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/460244 | Wiring board | Dec 12, 1999 | Issued |
| 09/402984 | WIRE FOR COMPOUND SUPERCONDUCTING CABLES AND METHOD OF PRODUCING THE SAME | Oct 13, 1999 | Abandoned |
Array
(
[id] => 4335430
[patent_doc_number] => 06313413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Wire structure of substrate for layout detection'
[patent_app_type] => 1
[patent_app_number] => 9/414584
[patent_app_country] => US
[patent_app_date] => 1999-10-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/313/06313413.pdf
[firstpage_image] =>[orig_patent_app_number] => 414584
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414584 | Wire structure of substrate for layout detection | Oct 7, 1999 | Issued |