Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2608030 [patent_doc_number] => 04922446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Apparatus and method for floating point normalization prediction' [patent_app_type] => 1 [patent_app_number] => 7/176612 [patent_app_country] => US [patent_app_date] => 1988-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3452 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922446.pdf [firstpage_image] =>[orig_patent_app_number] => 176612 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/176612
Apparatus and method for floating point normalization prediction Mar 31, 1988 Issued
Array ( [id] => 2531371 [patent_doc_number] => 04878193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Method and apparatus for accelerated addition of sliced addends' [patent_app_type] => 1 [patent_app_number] => 7/176594 [patent_app_country] => US [patent_app_date] => 1988-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2149 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878193.pdf [firstpage_image] =>[orig_patent_app_number] => 176594 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/176594
Method and apparatus for accelerated addition of sliced addends Mar 31, 1988 Issued
07/180665 METHOD OF CORRECTING ERRONEOUS VALUES OF SAMPLES OF AN EQUIDISTANTLY SAMPLED SIGNAL AND DEVICE FOR CARRYING OUT THE METHOD Mar 29, 1988 Abandoned
Array ( [id] => 2578658 [patent_doc_number] => 04901267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio' [patent_app_type] => 1 [patent_app_number] => 7/167802 [patent_app_country] => US [patent_app_date] => 1988-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 3169 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/901/04901267.pdf [firstpage_image] =>[orig_patent_app_number] => 167802 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/167802
Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio Mar 13, 1988 Issued
07/167732 SYSTOLIC FAST FOURIER TRANSFORM METHOD AND APPARATUS Mar 13, 1988 Abandoned
Array ( [id] => 2594690 [patent_doc_number] => 04891780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-02 [patent_title] => 'Divisional operation system for obtaining a quotient by repeated subtraction and shift operations' [patent_app_type] => 1 [patent_app_number] => 7/167173 [patent_app_country] => US [patent_app_date] => 1988-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2477 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/891/04891780.pdf [firstpage_image] =>[orig_patent_app_number] => 167173 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/167173
Divisional operation system for obtaining a quotient by repeated subtraction and shift operations Mar 10, 1988 Issued
07/166284 VERY-HIGH-SPEED FREQUENCY-DOMAIN FFT WINDOWING DEVICE Mar 9, 1988 Abandoned
Array ( [id] => 2482562 [patent_doc_number] => 04879676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-07 [patent_title] => 'Method and apparatus for precise floating point exceptions' [patent_app_type] => 1 [patent_app_number] => 7/161543 [patent_app_country] => US [patent_app_date] => 1988-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4000 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/879/04879676.pdf [firstpage_image] =>[orig_patent_app_number] => 161543 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/161543
Method and apparatus for precise floating point exceptions Feb 28, 1988 Issued
07/162081 CARRY GENERATION METHOD AND APPARATUS Feb 28, 1988 Abandoned
Array ( [id] => 2500451 [patent_doc_number] => 04860234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Portable keyboard operated alpha computer system with few keys and visual keystroke instructions' [patent_app_type] => 1 [patent_app_number] => 7/158653 [patent_app_country] => US [patent_app_date] => 1988-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3746 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860234.pdf [firstpage_image] =>[orig_patent_app_number] => 158653 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/158653
Portable keyboard operated alpha computer system with few keys and visual keystroke instructions Feb 21, 1988 Issued
Array ( [id] => 2483431 [patent_doc_number] => 04890229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-26 [patent_title] => 'Electronic baseball card' [patent_app_type] => 1 [patent_app_number] => 7/158193 [patent_app_country] => US [patent_app_date] => 1988-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2619 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/890/04890229.pdf [firstpage_image] =>[orig_patent_app_number] => 158193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/158193
Electronic baseball card Feb 18, 1988 Issued
Array ( [id] => 2484171 [patent_doc_number] => 04872133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-03 [patent_title] => 'Floating-point systolic array including serial processors' [patent_app_type] => 1 [patent_app_number] => 7/157682 [patent_app_country] => US [patent_app_date] => 1988-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2628 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/872/04872133.pdf [firstpage_image] =>[orig_patent_app_number] => 157682 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/157682
Floating-point systolic array including serial processors Feb 17, 1988 Issued
Array ( [id] => 2531336 [patent_doc_number] => 04878191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Multiplication circuit capable of operating at a high speed with a small amount of hardware' [patent_app_type] => 1 [patent_app_number] => 7/155771 [patent_app_country] => US [patent_app_date] => 1988-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2683 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878191.pdf [firstpage_image] =>[orig_patent_app_number] => 155771 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/155771
Multiplication circuit capable of operating at a high speed with a small amount of hardware Feb 15, 1988 Issued
Array ( [id] => 3029135 [patent_doc_number] => 05303172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Pipelined combination and vector signal processor' [patent_app_type] => 1 [patent_app_number] => 7/155671 [patent_app_country] => US [patent_app_date] => 1988-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 88 [patent_no_of_words] => 24214 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303172.pdf [firstpage_image] =>[orig_patent_app_number] => 155671 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/155671
Pipelined combination and vector signal processor Feb 15, 1988 Issued
Array ( [id] => 2494435 [patent_doc_number] => 04866647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-12 [patent_title] => 'Continuously variable digital delay circuit' [patent_app_type] => 1 [patent_app_number] => 7/152281 [patent_app_country] => US [patent_app_date] => 1988-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4132 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/866/04866647.pdf [firstpage_image] =>[orig_patent_app_number] => 152281 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/152281
Continuously variable digital delay circuit Feb 3, 1988 Issued
Array ( [id] => 2539117 [patent_doc_number] => 04839841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-13 [patent_title] => 'Programmable digital multiple event generator' [patent_app_type] => 1 [patent_app_number] => 7/150674 [patent_app_country] => US [patent_app_date] => 1988-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/839/04839841.pdf [firstpage_image] =>[orig_patent_app_number] => 150674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/150674
Programmable digital multiple event generator Jan 31, 1988 Issued
Array ( [id] => 2676725 [patent_doc_number] => 04935892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-19 [patent_title] => 'Divider and arithmetic processing units using signed digit operands' [patent_app_type] => 1 [patent_app_number] => 7/136365 [patent_app_country] => US [patent_app_date] => 1987-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6117 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 543 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/935/04935892.pdf [firstpage_image] =>[orig_patent_app_number] => 136365 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/136365
Divider and arithmetic processing units using signed digit operands Dec 21, 1987 Issued
07/122183 CHARACTER ENTRY DEVICE Nov 17, 1987 Abandoned
Array ( [id] => 2527552 [patent_doc_number] => 04870609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-26 [patent_title] => 'High speed full adder using complementary input-output signals' [patent_app_type] => 1 [patent_app_number] => 7/113612 [patent_app_country] => US [patent_app_date] => 1987-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3131 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/870/04870609.pdf [firstpage_image] =>[orig_patent_app_number] => 113612 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/113612
High speed full adder using complementary input-output signals Oct 25, 1987 Issued
Array ( [id] => 2495618 [patent_doc_number] => 04859985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Reconfigurable parameter filter having filter sections selectively operating independently on respective low precision binary numbers or together on a higher precision binary number' [patent_app_type] => 1 [patent_app_number] => 7/110272 [patent_app_country] => US [patent_app_date] => 1987-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1606 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/859/04859985.pdf [firstpage_image] =>[orig_patent_app_number] => 110272 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110272
Reconfigurable parameter filter having filter sections selectively operating independently on respective low precision binary numbers or together on a higher precision binary number Oct 19, 1987 Issued
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