Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2286673 [patent_doc_number] => 04602350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-22 [patent_title] => 'Data reordering memory for use in prime factor transform' [patent_app_type] => 1 [patent_app_number] => 6/776198 [patent_app_country] => US [patent_app_date] => 1985-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 23310 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/602/04602350.pdf [firstpage_image] =>[orig_patent_app_number] => 776198 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/776198
Data reordering memory for use in prime factor transform Sep 15, 1985 Issued
Array ( [id] => 2418243 [patent_doc_number] => 04761760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-02 [patent_title] => 'Digital adder-subtracter with tentative result correction circuit' [patent_app_type] => 1 [patent_app_number] => 6/767013 [patent_app_country] => US [patent_app_date] => 1985-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4634 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/761/04761760.pdf [firstpage_image] =>[orig_patent_app_number] => 767013 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/767013
Digital adder-subtracter with tentative result correction circuit Aug 18, 1985 Issued
06/767072 METHOD AND APPARATUS FOR REALIZING A LOGICAL OPERATION BY MODIFYING A FLOW OF ENERGY Aug 18, 1985 Abandoned
Array ( [id] => 2536068 [patent_doc_number] => RE032858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-07 [patent_title] => 'Stored-program control machine' [patent_app_type] => 2 [patent_app_number] => 6/766912 [patent_app_country] => US [patent_app_date] => 1985-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/032/RE032858.pdf [firstpage_image] =>[orig_patent_app_number] => 766912 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/766912
Stored-program control machine Aug 15, 1985 Issued
Array ( [id] => 2426789 [patent_doc_number] => 04748579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Method and circuit for performing discrete transforms' [patent_app_type] => 1 [patent_app_number] => 6/765918 [patent_app_country] => US [patent_app_date] => 1985-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 9 [patent_no_of_words] => 4872 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748579.pdf [firstpage_image] =>[orig_patent_app_number] => 765918 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/765918
Method and circuit for performing discrete transforms Aug 13, 1985 Issued
Array ( [id] => 2396295 [patent_doc_number] => 04764886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-16 [patent_title] => 'Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit' [patent_app_type] => 1 [patent_app_number] => 6/763117 [patent_app_country] => US [patent_app_date] => 1985-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 5991 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/764/04764886.pdf [firstpage_image] =>[orig_patent_app_number] => 763117 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/763117
Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit Aug 6, 1985 Issued
Array ( [id] => 2426863 [patent_doc_number] => 04748583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Cell-structured digital multiplier of semi-systolic construction' [patent_app_type] => 1 [patent_app_number] => 6/762444 [patent_app_country] => US [patent_app_date] => 1985-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4587 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748583.pdf [firstpage_image] =>[orig_patent_app_number] => 762444 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/762444
Cell-structured digital multiplier of semi-systolic construction Aug 4, 1985 Issued
Array ( [id] => 2359283 [patent_doc_number] => 04654857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-31 [patent_title] => 'Digital data processor with high reliability' [patent_app_type] => 1 [patent_app_number] => 6/762039 [patent_app_country] => US [patent_app_date] => 1985-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 33578 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/654/04654857.pdf [firstpage_image] =>[orig_patent_app_number] => 762039 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/762039
Digital data processor with high reliability Aug 1, 1985 Issued
Array ( [id] => 2346743 [patent_doc_number] => 04713790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-15 [patent_title] => 'Exclusive OR/NOR gate having cross-coupled transistors' [patent_app_type] => 1 [patent_app_number] => 6/760841 [patent_app_country] => US [patent_app_date] => 1985-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2039 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/713/04713790.pdf [firstpage_image] =>[orig_patent_app_number] => 760841 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/760841
Exclusive OR/NOR gate having cross-coupled transistors Jul 30, 1985 Issued
Array ( [id] => 2451388 [patent_doc_number] => 04722066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-26 [patent_title] => 'Digital signal overflow correction apparatus' [patent_app_type] => 1 [patent_app_number] => 6/760382 [patent_app_country] => US [patent_app_date] => 1985-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1729 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/722/04722066.pdf [firstpage_image] =>[orig_patent_app_number] => 760382 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/760382
Digital signal overflow correction apparatus Jul 29, 1985 Issued
Array ( [id] => 2388467 [patent_doc_number] => 04752902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-21 [patent_title] => 'Digital frequency synthesizer' [patent_app_type] => 1 [patent_app_number] => 6/752823 [patent_app_country] => US [patent_app_date] => 1985-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1829 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/752/04752902.pdf [firstpage_image] =>[orig_patent_app_number] => 752823 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/752823
Digital frequency synthesizer Jul 7, 1985 Issued
Array ( [id] => 2361078 [patent_doc_number] => 04688186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-18 [patent_title] => 'Division by a constant by iterative table lookup' [patent_app_type] => 1 [patent_app_number] => 6/752432 [patent_app_country] => US [patent_app_date] => 1985-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4715 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/688/04688186.pdf [firstpage_image] =>[orig_patent_app_number] => 752432 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/752432
Division by a constant by iterative table lookup Jul 7, 1985 Issued
Array ( [id] => 2322707 [patent_doc_number] => 04686643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-11 [patent_title] => 'Electronic equipment selectively storing a frequently used conversion function' [patent_app_type] => 1 [patent_app_number] => 6/750986 [patent_app_country] => US [patent_app_date] => 1985-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3117 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/686/04686643.pdf [firstpage_image] =>[orig_patent_app_number] => 750986 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/750986
Electronic equipment selectively storing a frequently used conversion function Jun 30, 1985 Issued
Array ( [id] => 2464366 [patent_doc_number] => 04718033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-05 [patent_title] => 'Intermediate decimal correction for sequential addition' [patent_app_type] => 1 [patent_app_number] => 6/750116 [patent_app_country] => US [patent_app_date] => 1985-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1370 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/718/04718033.pdf [firstpage_image] =>[orig_patent_app_number] => 750116 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/750116
Intermediate decimal correction for sequential addition Jun 27, 1985 Issued
Array ( [id] => 2450059 [patent_doc_number] => 04749982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-07 [patent_title] => 'Intelligent card' [patent_app_type] => 1 [patent_app_number] => 6/746200 [patent_app_country] => US [patent_app_date] => 1985-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 11128 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/749/04749982.pdf [firstpage_image] =>[orig_patent_app_number] => 746200 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/746200
Intelligent card Jun 17, 1985 Issued
Array ( [id] => 2262273 [patent_doc_number] => 04589083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-13 [patent_title] => 'Adaptive sinusoidal interference filter' [patent_app_type] => 1 [patent_app_number] => 6/744654 [patent_app_country] => US [patent_app_date] => 1985-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2725 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/589/04589083.pdf [firstpage_image] =>[orig_patent_app_number] => 744654 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/744654
Adaptive sinusoidal interference filter Jun 13, 1985 Issued
Array ( [id] => 2286609 [patent_doc_number] => 04623982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-18 [patent_title] => 'Conditional carry techniques for digital processors' [patent_app_type] => 1 [patent_app_number] => 6/742642 [patent_app_country] => US [patent_app_date] => 1985-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2528 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/623/04623982.pdf [firstpage_image] =>[orig_patent_app_number] => 742642 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/742642
Conditional carry techniques for digital processors Jun 9, 1985 Issued
Array ( [id] => 2247642 [patent_doc_number] => 04622648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-11 [patent_title] => 'Combinational logic structure using PASS transistors' [patent_app_type] => 1 [patent_app_number] => 6/732125 [patent_app_country] => US [patent_app_date] => 1985-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 73 [patent_no_of_words] => 5089 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/622/04622648.pdf [firstpage_image] =>[orig_patent_app_number] => 732125 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/732125
Combinational logic structure using PASS transistors May 7, 1985 Issued
90/000774 PROGRAMMABLE ARRAY LOGIC CIRCUIT May 1, 1985 Issued
Array ( [id] => 2426882 [patent_doc_number] => 04748584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Parallel multiplier utilizing Booth\'s algorithm' [patent_app_type] => 1 [patent_app_number] => 6/729661 [patent_app_country] => US [patent_app_date] => 1985-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4068 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748584.pdf [firstpage_image] =>[orig_patent_app_number] => 729661 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/729661
Parallel multiplier utilizing Booth's algorithm May 1, 1985 Issued
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