
David H. Malzahn
Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786 |
| Total Applications | 3174 |
| Issued Applications | 2743 |
| Pending Applications | 60 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2286673
[patent_doc_number] => 04602350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-07-22
[patent_title] => 'Data reordering memory for use in prime factor transform'
[patent_app_type] => 1
[patent_app_number] => 6/776198
[patent_app_country] => US
[patent_app_date] => 1985-09-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/602/04602350.pdf
[firstpage_image] =>[orig_patent_app_number] => 776198
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/776198 | Data reordering memory for use in prime factor transform | Sep 15, 1985 | Issued |
Array
(
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[patent_doc_number] => 04761760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-08-02
[patent_title] => 'Digital adder-subtracter with tentative result correction circuit'
[patent_app_type] => 1
[patent_app_number] => 6/767013
[patent_app_country] => US
[patent_app_date] => 1985-08-19
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 767013
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/767013 | Digital adder-subtracter with tentative result correction circuit | Aug 18, 1985 | Issued |
| 06/767072 | METHOD AND APPARATUS FOR REALIZING A LOGICAL OPERATION BY MODIFYING A FLOW OF ENERGY | Aug 18, 1985 | Abandoned |
Array
(
[id] => 2536068
[patent_doc_number] => RE032858
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[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Stored-program control machine'
[patent_app_type] => 2
[patent_app_number] => 6/766912
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/766912 | Stored-program control machine | Aug 15, 1985 | Issued |
Array
(
[id] => 2426789
[patent_doc_number] => 04748579
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[patent_kind] => NA
[patent_issue_date] => 1988-05-31
[patent_title] => 'Method and circuit for performing discrete transforms'
[patent_app_type] => 1
[patent_app_number] => 6/765918
[patent_app_country] => US
[patent_app_date] => 1985-08-14
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[firstpage_image] =>[orig_patent_app_number] => 765918
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/765918 | Method and circuit for performing discrete transforms | Aug 13, 1985 | Issued |
Array
(
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[patent_doc_number] => 04764886
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[patent_kind] => NA
[patent_issue_date] => 1988-08-16
[patent_title] => 'Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit'
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[patent_app_number] => 6/763117
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[firstpage_image] =>[orig_patent_app_number] => 763117
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/763117 | Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit | Aug 6, 1985 | Issued |
Array
(
[id] => 2426863
[patent_doc_number] => 04748583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-05-31
[patent_title] => 'Cell-structured digital multiplier of semi-systolic construction'
[patent_app_type] => 1
[patent_app_number] => 6/762444
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[patent_app_date] => 1985-08-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/762444 | Cell-structured digital multiplier of semi-systolic construction | Aug 4, 1985 | Issued |
Array
(
[id] => 2359283
[patent_doc_number] => 04654857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-31
[patent_title] => 'Digital data processor with high reliability'
[patent_app_type] => 1
[patent_app_number] => 6/762039
[patent_app_country] => US
[patent_app_date] => 1985-08-02
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[firstpage_image] =>[orig_patent_app_number] => 762039
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/762039 | Digital data processor with high reliability | Aug 1, 1985 | Issued |
Array
(
[id] => 2346743
[patent_doc_number] => 04713790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-15
[patent_title] => 'Exclusive OR/NOR gate having cross-coupled transistors'
[patent_app_type] => 1
[patent_app_number] => 6/760841
[patent_app_country] => US
[patent_app_date] => 1985-07-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/713/04713790.pdf
[firstpage_image] =>[orig_patent_app_number] => 760841
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/760841 | Exclusive OR/NOR gate having cross-coupled transistors | Jul 30, 1985 | Issued |
Array
(
[id] => 2451388
[patent_doc_number] => 04722066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-01-26
[patent_title] => 'Digital signal overflow correction apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/760382
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[patent_app_date] => 1985-07-30
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[pdf_file] => patents/04/722/04722066.pdf
[firstpage_image] =>[orig_patent_app_number] => 760382
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/760382 | Digital signal overflow correction apparatus | Jul 29, 1985 | Issued |
Array
(
[id] => 2388467
[patent_doc_number] => 04752902
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[patent_kind] => NA
[patent_issue_date] => 1988-06-21
[patent_title] => 'Digital frequency synthesizer'
[patent_app_type] => 1
[patent_app_number] => 6/752823
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[patent_app_date] => 1985-07-08
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[pdf_file] => patents/04/752/04752902.pdf
[firstpage_image] =>[orig_patent_app_number] => 752823
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/752823 | Digital frequency synthesizer | Jul 7, 1985 | Issued |
Array
(
[id] => 2361078
[patent_doc_number] => 04688186
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[patent_kind] => NA
[patent_issue_date] => 1987-08-18
[patent_title] => 'Division by a constant by iterative table lookup'
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[pdf_file] => patents/04/688/04688186.pdf
[firstpage_image] =>[orig_patent_app_number] => 752432
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/752432 | Division by a constant by iterative table lookup | Jul 7, 1985 | Issued |
Array
(
[id] => 2322707
[patent_doc_number] => 04686643
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[patent_kind] => NA
[patent_issue_date] => 1987-08-11
[patent_title] => 'Electronic equipment selectively storing a frequently used conversion function'
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[firstpage_image] =>[orig_patent_app_number] => 750986
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/750986 | Electronic equipment selectively storing a frequently used conversion function | Jun 30, 1985 | Issued |
Array
(
[id] => 2464366
[patent_doc_number] => 04718033
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[patent_issue_date] => 1988-01-05
[patent_title] => 'Intermediate decimal correction for sequential addition'
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[firstpage_image] =>[orig_patent_app_number] => 750116
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/750116 | Intermediate decimal correction for sequential addition | Jun 27, 1985 | Issued |
Array
(
[id] => 2450059
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[patent_title] => 'Intelligent card'
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[pdf_file] => patents/04/749/04749982.pdf
[firstpage_image] =>[orig_patent_app_number] => 746200
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/746200 | Intelligent card | Jun 17, 1985 | Issued |
Array
(
[id] => 2262273
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[patent_issue_date] => 1986-05-13
[patent_title] => 'Adaptive sinusoidal interference filter'
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[firstpage_image] =>[orig_patent_app_number] => 744654
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/744654 | Adaptive sinusoidal interference filter | Jun 13, 1985 | Issued |
Array
(
[id] => 2286609
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[patent_title] => 'Conditional carry techniques for digital processors'
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[firstpage_image] =>[orig_patent_app_number] => 742642
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/742642 | Conditional carry techniques for digital processors | Jun 9, 1985 | Issued |
Array
(
[id] => 2247642
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[patent_issue_date] => 1986-11-11
[patent_title] => 'Combinational logic structure using PASS transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/732125 | Combinational logic structure using PASS transistors | May 7, 1985 | Issued |
| 90/000774 | PROGRAMMABLE ARRAY LOGIC CIRCUIT | May 1, 1985 | Issued |
Array
(
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[patent_title] => 'Parallel multiplier utilizing Booth\'s algorithm'
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