Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2392867 [patent_doc_number] => 04707799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-11-17 [patent_title] => 'Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction' [patent_app_type] => 1 [patent_app_number] => 6/695346 [patent_app_country] => US [patent_app_date] => 1985-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8293 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/707/04707799.pdf [firstpage_image] =>[orig_patent_app_number] => 695346 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/695346
Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction Jan 27, 1985 Issued
Array ( [id] => 2308975 [patent_doc_number] => 04685077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-04 [patent_title] => 'Data processing apparatus having binary multiplication capability' [patent_app_type] => 1 [patent_app_number] => 6/692348 [patent_app_country] => US [patent_app_date] => 1985-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2125 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/685/04685077.pdf [firstpage_image] =>[orig_patent_app_number] => 692348 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/692348
Data processing apparatus having binary multiplication capability Jan 16, 1985 Issued
Array ( [id] => 2428720 [patent_doc_number] => 04734875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-29 [patent_title] => 'Log mixer circuit' [patent_app_type] => 1 [patent_app_number] => 6/690213 [patent_app_country] => US [patent_app_date] => 1985-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2496 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/734/04734875.pdf [firstpage_image] =>[orig_patent_app_number] => 690213 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/690213
Log mixer circuit Jan 8, 1985 Issued
Array ( [id] => 2324908 [patent_doc_number] => 04689763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-25 [patent_title] => 'CMOS full adder circuit' [patent_app_type] => 1 [patent_app_number] => 6/688782 [patent_app_country] => US [patent_app_date] => 1985-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2369 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/689/04689763.pdf [firstpage_image] =>[orig_patent_app_number] => 688782 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/688782
CMOS full adder circuit Jan 3, 1985 Issued
Array ( [id] => 2427832 [patent_doc_number] => 04727507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-23 [patent_title] => 'Multiplication circuit using a multiplier and a carry propagating adder' [patent_app_type] => 1 [patent_app_number] => 6/685517 [patent_app_country] => US [patent_app_date] => 1984-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4005 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/727/04727507.pdf [firstpage_image] =>[orig_patent_app_number] => 685517 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/685517
Multiplication circuit using a multiplier and a carry propagating adder Dec 23, 1984 Issued
Array ( [id] => 2274009 [patent_doc_number] => 04584556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-22 [patent_title] => 'Ratio comparator for digital signals' [patent_app_type] => 1 [patent_app_number] => 6/684168 [patent_app_country] => US [patent_app_date] => 1984-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5064 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/584/04584556.pdf [firstpage_image] =>[orig_patent_app_number] => 684168 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/684168
Ratio comparator for digital signals Dec 20, 1984 Issued
Array ( [id] => 2301870 [patent_doc_number] => 04697248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-29 [patent_title] => 'Arithmetic circuit for obtaining the vector product of two vectors' [patent_app_type] => 1 [patent_app_number] => 6/685125 [patent_app_country] => US [patent_app_date] => 1984-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4085 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/697/04697248.pdf [firstpage_image] =>[orig_patent_app_number] => 685125 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/685125
Arithmetic circuit for obtaining the vector product of two vectors Dec 20, 1984 Issued
Array ( [id] => 2333273 [patent_doc_number] => 04706210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-11-10 [patent_title] => 'Guild array multiplier for binary numbers in two\'s complement notation' [patent_app_type] => 1 [patent_app_number] => 6/681158 [patent_app_country] => US [patent_app_date] => 1984-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/706/04706210.pdf [firstpage_image] =>[orig_patent_app_number] => 681158 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/681158
Guild array multiplier for binary numbers in two's complement notation Dec 12, 1984 Issued
06/678938 FLOATING-POINT ADDITION/SUBTRACTION SYSTEM WITH DIGIT POSITION ALIGNMENT BETWEEN FRACTIONS OF MULTIPLE SETS OF DATA Dec 5, 1984 Abandoned
Array ( [id] => 2422495 [patent_doc_number] => 04744042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-10 [patent_title] => 'Transform processor system having post processing' [patent_app_type] => 1 [patent_app_number] => 6/676769 [patent_app_country] => US [patent_app_date] => 1984-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 15553 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 34 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/744/04744042.pdf [firstpage_image] =>[orig_patent_app_number] => 676769 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/676769
Transform processor system having post processing Nov 29, 1984 Issued
Array ( [id] => 2340382 [patent_doc_number] => 04701877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'Highspeed parallel adder with clocked switching circuits' [patent_app_type] => 1 [patent_app_number] => 6/675303 [patent_app_country] => US [patent_app_date] => 1984-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 2736 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701877.pdf [firstpage_image] =>[orig_patent_app_number] => 675303 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/675303
Highspeed parallel adder with clocked switching circuits Nov 26, 1984 Issued
Array ( [id] => 2340355 [patent_doc_number] => 04701875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'High speed convolution arithmetic circuit with multiple counters' [patent_app_type] => 1 [patent_app_number] => 6/674844 [patent_app_country] => US [patent_app_date] => 1984-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10913 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701875.pdf [firstpage_image] =>[orig_patent_app_number] => 674844 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/674844
High speed convolution arithmetic circuit with multiple counters Nov 25, 1984 Issued
Array ( [id] => 2426771 [patent_doc_number] => 04748578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Process and apparatus for translating the sampling rate of a sampling sequence' [patent_app_type] => 1 [patent_app_number] => 6/674633 [patent_app_country] => US [patent_app_date] => 1984-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8086 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748578.pdf [firstpage_image] =>[orig_patent_app_number] => 674633 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/674633
Process and apparatus for translating the sampling rate of a sampling sequence Nov 25, 1984 Issued
06/674624 SQUARED-RADIX DISCRETE FOURIER TRANSFORM Nov 25, 1984 Abandoned
Array ( [id] => 2423213 [patent_doc_number] => 04736335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-05 [patent_title] => 'Multiplier-accumulator circuit using latched sums and carries' [patent_app_type] => 1 [patent_app_number] => 6/670222 [patent_app_country] => US [patent_app_date] => 1984-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2594 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/736/04736335.pdf [firstpage_image] =>[orig_patent_app_number] => 670222 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/670222
Multiplier-accumulator circuit using latched sums and carries Nov 12, 1984 Issued
Array ( [id] => 2464387 [patent_doc_number] => 04718034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-05 [patent_title] => 'Carry-save propagate adder' [patent_app_type] => 1 [patent_app_number] => 6/670401 [patent_app_country] => US [patent_app_date] => 1984-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9152 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/718/04718034.pdf [firstpage_image] =>[orig_patent_app_number] => 670401 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/670401
Carry-save propagate adder Nov 7, 1984 Issued
Array ( [id] => 2355482 [patent_doc_number] => 04692891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-08 [patent_title] => 'Coded decimal non-restoring divider' [patent_app_type] => 1 [patent_app_number] => 6/668842 [patent_app_country] => US [patent_app_date] => 1984-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3725 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/692/04692891.pdf [firstpage_image] =>[orig_patent_app_number] => 668842 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/668842
Coded decimal non-restoring divider Nov 5, 1984 Issued
90/000659 DIGITALLY DETERMINED VELOCITY CONTROL METHOD AND MEANS FOR A DIGITAL MOTOR SYSTEM Oct 31, 1984 Issued
Array ( [id] => 2308988 [patent_doc_number] => 04685078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-04 [patent_title] => 'Dual incrementor' [patent_app_type] => 1 [patent_app_number] => 6/666703 [patent_app_country] => US [patent_app_date] => 1984-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3220 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/685/04685078.pdf [firstpage_image] =>[orig_patent_app_number] => 666703 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/666703
Dual incrementor Oct 30, 1984 Issued
06/666216 MICROPROCESSOR HAVING MULTIPLICATION CIRCUITRY IMPLEMENTING A MODIFIED BOOTH ALGORITHM Oct 29, 1984 Abandoned
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