| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_title] => 'Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction'
[patent_app_type] => 1
[patent_app_number] => 6/695346
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Array
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[patent_issue_date] => 1987-08-04
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[patent_app_number] => 6/692348
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/692348 | Data processing apparatus having binary multiplication capability | Jan 16, 1985 | Issued |
Array
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[patent_doc_number] => 04734875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-03-29
[patent_title] => 'Log mixer circuit'
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[patent_app_number] => 6/690213
[patent_app_country] => US
[patent_app_date] => 1985-01-09
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Array
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[patent_doc_number] => 04689763
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[patent_issue_date] => 1987-08-25
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[patent_app_type] => 1
[patent_app_number] => 6/688782
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[patent_app_date] => 1985-01-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/688782 | CMOS full adder circuit | Jan 3, 1985 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1988-02-23
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[patent_app_date] => 1984-12-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/685517 | Multiplication circuit using a multiplier and a carry propagating adder | Dec 23, 1984 | Issued |
Array
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[patent_doc_number] => 04584556
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[patent_kind] => NA
[patent_issue_date] => 1986-04-22
[patent_title] => 'Ratio comparator for digital signals'
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[patent_app_number] => 6/684168
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Array
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[id] => 2301870
[patent_doc_number] => 04697248
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[patent_kind] => NA
[patent_issue_date] => 1987-09-29
[patent_title] => 'Arithmetic circuit for obtaining the vector product of two vectors'
[patent_app_type] => 1
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[patent_app_date] => 1984-12-21
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[firstpage_image] =>[orig_patent_app_number] => 685125
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/685125 | Arithmetic circuit for obtaining the vector product of two vectors | Dec 20, 1984 | Issued |
Array
(
[id] => 2333273
[patent_doc_number] => 04706210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-11-10
[patent_title] => 'Guild array multiplier for binary numbers in two\'s complement notation'
[patent_app_type] => 1
[patent_app_number] => 6/681158
[patent_app_country] => US
[patent_app_date] => 1984-12-13
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[pdf_file] => patents/04/706/04706210.pdf
[firstpage_image] =>[orig_patent_app_number] => 681158
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/681158 | Guild array multiplier for binary numbers in two's complement notation | Dec 12, 1984 | Issued |
| 06/678938 | FLOATING-POINT ADDITION/SUBTRACTION SYSTEM WITH DIGIT POSITION ALIGNMENT BETWEEN FRACTIONS OF MULTIPLE SETS OF DATA | Dec 5, 1984 | Abandoned |
Array
(
[id] => 2422495
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[patent_issue_date] => 1988-05-10
[patent_title] => 'Transform processor system having post processing'
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[patent_app_number] => 6/676769
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/676769 | Transform processor system having post processing | Nov 29, 1984 | Issued |
Array
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[patent_issue_date] => 1987-10-20
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[patent_app_number] => 6/675303
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[patent_app_date] => 1984-11-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/675303 | Highspeed parallel adder with clocked switching circuits | Nov 26, 1984 | Issued |
Array
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[id] => 2340355
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[patent_issue_date] => 1987-10-20
[patent_title] => 'High speed convolution arithmetic circuit with multiple counters'
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[patent_app_number] => 6/674844
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[patent_app_date] => 1984-11-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/674844 | High speed convolution arithmetic circuit with multiple counters | Nov 25, 1984 | Issued |
Array
(
[id] => 2426771
[patent_doc_number] => 04748578
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[patent_kind] => NA
[patent_issue_date] => 1988-05-31
[patent_title] => 'Process and apparatus for translating the sampling rate of a sampling sequence'
[patent_app_type] => 1
[patent_app_number] => 6/674633
[patent_app_country] => US
[patent_app_date] => 1984-11-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/674633 | Process and apparatus for translating the sampling rate of a sampling sequence | Nov 25, 1984 | Issued |
| 06/674624 | SQUARED-RADIX DISCRETE FOURIER TRANSFORM | Nov 25, 1984 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 06/670222 | Multiplier-accumulator circuit using latched sums and carries | Nov 12, 1984 | Issued |
Array
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[patent_issue_date] => 1988-01-05
[patent_title] => 'Carry-save propagate adder'
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[firstpage_image] =>[orig_patent_app_number] => 670401
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/670401 | Carry-save propagate adder | Nov 7, 1984 | Issued |
Array
(
[id] => 2355482
[patent_doc_number] => 04692891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-08
[patent_title] => 'Coded decimal non-restoring divider'
[patent_app_type] => 1
[patent_app_number] => 6/668842
[patent_app_country] => US
[patent_app_date] => 1984-11-06
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[firstpage_image] =>[orig_patent_app_number] => 668842
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/668842 | Coded decimal non-restoring divider | Nov 5, 1984 | Issued |
| 90/000659 | DIGITALLY DETERMINED VELOCITY CONTROL METHOD AND MEANS FOR A DIGITAL MOTOR SYSTEM | Oct 31, 1984 | Issued |
Array
(
[id] => 2308988
[patent_doc_number] => 04685078
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-08-04
[patent_title] => 'Dual incrementor'
[patent_app_type] => 1
[patent_app_number] => 6/666703
[patent_app_country] => US
[patent_app_date] => 1984-10-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 666703
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/666703 | Dual incrementor | Oct 30, 1984 | Issued |
| 06/666216 | MICROPROCESSOR HAVING MULTIPLICATION CIRCUITRY IMPLEMENTING A MODIFIED BOOTH ALGORITHM | Oct 29, 1984 | Abandoned |