Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2355449 [patent_doc_number] => 04692888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-08 [patent_title] => 'Method and apparatus for generating and summing the products of pairs of numbers' [patent_app_type] => 1 [patent_app_number] => 6/657563 [patent_app_country] => US [patent_app_date] => 1984-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1910 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/692/04692888.pdf [firstpage_image] =>[orig_patent_app_number] => 657563 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/657563
Method and apparatus for generating and summing the products of pairs of numbers Oct 2, 1984 Issued
Array ( [id] => 2308956 [patent_doc_number] => 04685076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-04 [patent_title] => 'Vector processor for processing one vector instruction with a plurality of vector processing units' [patent_app_type] => 1 [patent_app_number] => 6/657354 [patent_app_country] => US [patent_app_date] => 1984-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4376 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/685/04685076.pdf [firstpage_image] =>[orig_patent_app_number] => 657354 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/657354
Vector processor for processing one vector instruction with a plurality of vector processing units Oct 2, 1984 Issued
Array ( [id] => 2340372 [patent_doc_number] => 04701876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'Digital data processor for multiplying data by a coefficient set' [patent_app_type] => 1 [patent_app_number] => 6/651312 [patent_app_country] => US [patent_app_date] => 1984-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 10528 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701876.pdf [firstpage_image] =>[orig_patent_app_number] => 651312 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/651312
Digital data processor for multiplying data by a coefficient set Sep 16, 1984 Issued
Array ( [id] => 2324896 [patent_doc_number] => 04689762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-25 [patent_title] => 'Dynamically configurable fast Fourier transform butterfly circuit' [patent_app_type] => 1 [patent_app_number] => 6/649029 [patent_app_country] => US [patent_app_date] => 1984-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6564 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/689/04689762.pdf [firstpage_image] =>[orig_patent_app_number] => 649029 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/649029
Dynamically configurable fast Fourier transform butterfly circuit Sep 9, 1984 Issued
Array ( [id] => 2391611 [patent_doc_number] => 04695970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-22 [patent_title] => 'Linear predictive coding technique with interleaved sequence digital lattice filter' [patent_app_type] => 1 [patent_app_number] => 6/646869 [patent_app_country] => US [patent_app_date] => 1984-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/695/04695970.pdf [firstpage_image] =>[orig_patent_app_number] => 646869 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/646869
Linear predictive coding technique with interleaved sequence digital lattice filter Aug 30, 1984 Issued
Array ( [id] => 2320898 [patent_doc_number] => 04700323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-13 [patent_title] => 'Digital lattice filter with multiplexed full adder' [patent_app_type] => 1 [patent_app_number] => 6/646868 [patent_app_country] => US [patent_app_date] => 1984-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 9580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/700/04700323.pdf [firstpage_image] =>[orig_patent_app_number] => 646868 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/646868
Digital lattice filter with multiplexed full adder Aug 30, 1984 Issued
Array ( [id] => 2322718 [patent_doc_number] => 04686644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-11 [patent_title] => 'Linear predictive coding technique with symmetrical calculation of Y-and B-values' [patent_app_type] => 1 [patent_app_number] => 6/646606 [patent_app_country] => US [patent_app_date] => 1984-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 11161 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/686/04686644.pdf [firstpage_image] =>[orig_patent_app_number] => 646606 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/646606
Linear predictive coding technique with symmetrical calculation of Y-and B-values Aug 30, 1984 Issued
Array ( [id] => 2452735 [patent_doc_number] => 04740906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-26 [patent_title] => 'Digital lattice filter with multiplexed fast adder/full adder for performing sequential multiplication and addition operations' [patent_app_type] => 1 [patent_app_number] => 6/646381 [patent_app_country] => US [patent_app_date] => 1984-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 15617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/740/04740906.pdf [firstpage_image] =>[orig_patent_app_number] => 646381 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/646381
Digital lattice filter with multiplexed fast adder/full adder for performing sequential multiplication and addition operations Aug 30, 1984 Issued
Array ( [id] => 2343148 [patent_doc_number] => 04677583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-30 [patent_title] => 'Apparatus for decimal multiplication' [patent_app_type] => 1 [patent_app_number] => 6/625131 [patent_app_country] => US [patent_app_date] => 1984-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 11395 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/677/04677583.pdf [firstpage_image] =>[orig_patent_app_number] => 625131 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/625131
Apparatus for decimal multiplication Jun 26, 1984 Issued
Array ( [id] => 2335140 [patent_doc_number] => 04672568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-09 [patent_title] => 'Method for digital voltage controlled oscillator' [patent_app_type] => 1 [patent_app_number] => 6/620993 [patent_app_country] => US [patent_app_date] => 1984-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3587 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/672/04672568.pdf [firstpage_image] =>[orig_patent_app_number] => 620993 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/620993
Method for digital voltage controlled oscillator Jun 14, 1984 Issued
Array ( [id] => 2360749 [patent_doc_number] => 04651301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-17 [patent_title] => 'Circuit arrangement for performing rapid sortation or selection according to rank' [patent_app_type] => 1 [patent_app_number] => 6/620130 [patent_app_country] => US [patent_app_date] => 1984-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1907 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/651/04651301.pdf [firstpage_image] =>[orig_patent_app_number] => 620130 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/620130
Circuit arrangement for performing rapid sortation or selection according to rank Jun 12, 1984 Issued
Array ( [id] => 2317197 [patent_doc_number] => 04675837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-23 [patent_title] => 'Digital arithmetic unit having shortened processing time and a simplified structure' [patent_app_type] => 1 [patent_app_number] => 6/619185 [patent_app_country] => US [patent_app_date] => 1984-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3852 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/675/04675837.pdf [firstpage_image] =>[orig_patent_app_number] => 619185 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/619185
Digital arithmetic unit having shortened processing time and a simplified structure Jun 10, 1984 Issued
Array ( [id] => 2271072 [patent_doc_number] => 04575812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-11 [patent_title] => 'X.times.Y Bit array multiplier/accumulator circuit' [patent_app_type] => 1 [patent_app_number] => 6/615989 [patent_app_country] => US [patent_app_date] => 1984-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 9656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/575/04575812.pdf [firstpage_image] =>[orig_patent_app_number] => 615989 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/615989
X.times.Y Bit array multiplier/accumulator circuit May 30, 1984 Issued
06/614911 NORMALIZING CIRCUIT May 28, 1984 Abandoned
Array ( [id] => 2355470 [patent_doc_number] => 04692890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-08 [patent_title] => 'Method and integrator circuit for integrating signals, in particular for scintillation gamma camera' [patent_app_type] => 1 [patent_app_number] => 6/614886 [patent_app_country] => US [patent_app_date] => 1984-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9046 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/692/04692890.pdf [firstpage_image] =>[orig_patent_app_number] => 614886 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/614886
Method and integrator circuit for integrating signals, in particular for scintillation gamma camera May 28, 1984 Issued
Array ( [id] => 2391859 [patent_doc_number] => 04695983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-22 [patent_title] => 'Calculator or pocket computer with selectable operational sequence' [patent_app_type] => 1 [patent_app_number] => 6/614135 [patent_app_country] => US [patent_app_date] => 1984-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2180 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/695/04695983.pdf [firstpage_image] =>[orig_patent_app_number] => 614135 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/614135
Calculator or pocket computer with selectable operational sequence May 24, 1984 Issued
Array ( [id] => 2364886 [patent_doc_number] => 04648057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-03 [patent_title] => 'Robust iterative technique for high-resolution spatial processing and spectral estimation' [patent_app_type] => 1 [patent_app_number] => 6/611811 [patent_app_country] => US [patent_app_date] => 1984-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3229 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/648/04648057.pdf [firstpage_image] =>[orig_patent_app_number] => 611811 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/611811
Robust iterative technique for high-resolution spatial processing and spectral estimation May 17, 1984 Issued
Array ( [id] => 2360677 [patent_doc_number] => 04651294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-17 [patent_title] => 'Electronic function calculator with improved functional command entry' [patent_app_type] => 1 [patent_app_number] => 6/610645 [patent_app_country] => US [patent_app_date] => 1984-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1296 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/651/04651294.pdf [firstpage_image] =>[orig_patent_app_number] => 610645 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/610645
Electronic function calculator with improved functional command entry May 15, 1984 Issued
Array ( [id] => 2360705 [patent_doc_number] => 04651296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-17 [patent_title] => 'High speed CMOS FET full-adder circuit' [patent_app_type] => 1 [patent_app_number] => 6/609114 [patent_app_country] => US [patent_app_date] => 1984-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3279 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/651/04651296.pdf [firstpage_image] =>[orig_patent_app_number] => 609114 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/609114
High speed CMOS FET full-adder circuit May 10, 1984 Issued
Array ( [id] => 2393518 [patent_doc_number] => 04724528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-09 [patent_title] => 'Battery charge level monitor in a computer system' [patent_app_type] => 1 [patent_app_number] => 6/608317 [patent_app_country] => US [patent_app_date] => 1984-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 971 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/724/04724528.pdf [firstpage_image] =>[orig_patent_app_number] => 608317 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/608317
Battery charge level monitor in a computer system May 7, 1984 Issued
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