Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2260109 [patent_doc_number] => 04563751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-01-07 [patent_title] => 'Carry propagate adder circuit which differentially senses a carry input' [patent_app_type] => 1 [patent_app_number] => 6/604252 [patent_app_country] => US [patent_app_date] => 1984-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2233 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/563/04563751.pdf [firstpage_image] =>[orig_patent_app_number] => 604252 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/604252
Carry propagate adder circuit which differentially senses a carry input Apr 25, 1984 Issued
Array ( [id] => 2364774 [patent_doc_number] => 04667303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-05-19 [patent_title] => 'Digital integrated circuit comprising complementary field effect transistors' [patent_app_type] => 1 [patent_app_number] => 6/600051 [patent_app_country] => US [patent_app_date] => 1984-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4322 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/667/04667303.pdf [firstpage_image] =>[orig_patent_app_number] => 600051 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/600051
Digital integrated circuit comprising complementary field effect transistors Apr 12, 1984 Issued
Array ( [id] => 2223276 [patent_doc_number] => 04621338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-04 [patent_title] => 'CMOS adder using exclusive OR and/or exclusive-NOR gates' [patent_app_type] => 1 [patent_app_number] => 6/600169 [patent_app_country] => US [patent_app_date] => 1984-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2155 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/621/04621338.pdf [firstpage_image] =>[orig_patent_app_number] => 600169 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/600169
CMOS adder using exclusive OR and/or exclusive-NOR gates Apr 12, 1984 Issued
Array ( [id] => 2309433 [patent_doc_number] => 04644490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-17 [patent_title] => 'Floating point data adder' [patent_app_type] => 1 [patent_app_number] => 6/599167 [patent_app_country] => US [patent_app_date] => 1984-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3544 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/644/04644490.pdf [firstpage_image] =>[orig_patent_app_number] => 599167 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/599167
Floating point data adder Apr 10, 1984 Issued
06/599119 ORTHOGONAL TRANSFORMER AND APPARATUS OPERATIONAL THEREBY Apr 10, 1984 Abandoned
Array ( [id] => 2364422 [patent_doc_number] => 04665500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-05-12 [patent_title] => 'Multiply and divide unit for a high speed processor' [patent_app_type] => 1 [patent_app_number] => 6/598941 [patent_app_country] => US [patent_app_date] => 1984-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 25081 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/665/04665500.pdf [firstpage_image] =>[orig_patent_app_number] => 598941 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/598941
Multiply and divide unit for a high speed processor Apr 10, 1984 Issued
Array ( [id] => 2364888 [patent_doc_number] => 04648058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-03 [patent_title] => 'Look-ahead rounding circuit' [patent_app_type] => 1 [patent_app_number] => 6/596484 [patent_app_country] => US [patent_app_date] => 1984-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2936 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/648/04648058.pdf [firstpage_image] =>[orig_patent_app_number] => 596484 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/596484
Look-ahead rounding circuit Apr 2, 1984 Issued
Array ( [id] => 2299437 [patent_doc_number] => 04660165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-04-21 [patent_title] => 'Pyramid carry adder circuit' [patent_app_type] => 1 [patent_app_number] => 6/596485 [patent_app_country] => US [patent_app_date] => 1984-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5208 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/660/04660165.pdf [firstpage_image] =>[orig_patent_app_number] => 596485 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/596485
Pyramid carry adder circuit Apr 2, 1984 Issued
Array ( [id] => 2297777 [patent_doc_number] => 04639888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-27 [patent_title] => 'Circuit arrangement for accelerated carry formation in an adder device' [patent_app_type] => 1 [patent_app_number] => 6/595241 [patent_app_country] => US [patent_app_date] => 1984-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 6527 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/639/04639888.pdf [firstpage_image] =>[orig_patent_app_number] => 595241 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/595241
Circuit arrangement for accelerated carry formation in an adder device Mar 29, 1984 Issued
06/591357 DOPPLER AGC USING OVERFLOW COUNTERS INTERNAL TO FFT Mar 19, 1984 Abandoned
Array ( [id] => 2317783 [patent_doc_number] => 04646256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-24 [patent_title] => 'Computer and method for the discrete bracewell transform' [patent_app_type] => 1 [patent_app_number] => 6/590885 [patent_app_country] => US [patent_app_date] => 1984-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 12072 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/646/04646256.pdf [firstpage_image] =>[orig_patent_app_number] => 590885 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/590885
Computer and method for the discrete bracewell transform Mar 18, 1984 Issued
Array ( [id] => 2182678 [patent_doc_number] => 04562553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-31 [patent_title] => 'Floating point arithmetic system and method with rounding anticipation' [patent_app_type] => 1 [patent_app_number] => 6/591199 [patent_app_country] => US [patent_app_date] => 1984-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4414 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/562/04562553.pdf [firstpage_image] =>[orig_patent_app_number] => 591199 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/591199
Floating point arithmetic system and method with rounding anticipation Mar 18, 1984 Issued
Array ( [id] => 2290879 [patent_doc_number] => 04604720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-05 [patent_title] => 'Interpolating filter arrangement with non-rational ratio between the input and the output sampling frequencies' [patent_app_type] => 1 [patent_app_number] => 6/590096 [patent_app_country] => US [patent_app_date] => 1984-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5340 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/604/04604720.pdf [firstpage_image] =>[orig_patent_app_number] => 590096 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/590096
Interpolating filter arrangement with non-rational ratio between the input and the output sampling frequencies Mar 15, 1984 Issued
Array ( [id] => 2138652 [patent_doc_number] => 04551815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-05 [patent_title] => 'Functionally redundant logic network architectures with logic selection means' [patent_app_type] => 1 [patent_app_number] => 6/589943 [patent_app_country] => US [patent_app_date] => 1984-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 15179 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/551/04551815.pdf [firstpage_image] =>[orig_patent_app_number] => 589943 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/589943
Functionally redundant logic network architectures with logic selection means Mar 14, 1984 Issued
Array ( [id] => 2163959 [patent_doc_number] => 04521868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-06-04 [patent_title] => 'Electronic data processing apparatus with equation operating system having improved exponentiation operators' [patent_app_type] => 1 [patent_app_number] => 6/584841 [patent_app_country] => US [patent_app_date] => 1984-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7291 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/521/04521868.pdf [firstpage_image] =>[orig_patent_app_number] => 584841 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/584841
Electronic data processing apparatus with equation operating system having improved exponentiation operators Feb 28, 1984 Issued
Array ( [id] => 2160763 [patent_doc_number] => 04519045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-05-21 [patent_title] => 'Electronic data processing apparatus with equation operating system having improved unary operation implementation' [patent_app_type] => 1 [patent_app_number] => 6/584707 [patent_app_country] => US [patent_app_date] => 1984-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7194 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/519/04519045.pdf [firstpage_image] =>[orig_patent_app_number] => 584707 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/584707
Electronic data processing apparatus with equation operating system having improved unary operation implementation Feb 28, 1984 Issued
Array ( [id] => 2298276 [patent_doc_number] => 04639920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-27 [patent_title] => 'Data interpolating circuit using a two data word memory' [patent_app_type] => 1 [patent_app_number] => 6/584262 [patent_app_country] => US [patent_app_date] => 1984-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6757 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/639/04639920.pdf [firstpage_image] =>[orig_patent_app_number] => 584262 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/584262
Data interpolating circuit using a two data word memory Feb 26, 1984 Issued
Array ( [id] => 2297766 [patent_doc_number] => 04639887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-27 [patent_title] => 'Bifurcated method and apparatus for floating point addition with decreased latency time' [patent_app_type] => 1 [patent_app_number] => 6/583531 [patent_app_country] => US [patent_app_date] => 1984-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7762 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/639/04639887.pdf [firstpage_image] =>[orig_patent_app_number] => 583531 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/583531
Bifurcated method and apparatus for floating point addition with decreased latency time Feb 23, 1984 Issued
06/580223 PROGRAMMABLE FUNCTION CONTROLLER FOR USE IN A WAVEFORM GENERATOR SYSTEM Feb 14, 1984 Abandoned
Array ( [id] => 2309420 [patent_doc_number] => 04644489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-17 [patent_title] => 'Multi-format binary coded decimal processor with selective output formatting' [patent_app_type] => 1 [patent_app_number] => 6/579091 [patent_app_country] => US [patent_app_date] => 1984-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/644/04644489.pdf [firstpage_image] =>[orig_patent_app_number] => 579091 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/579091
Multi-format binary coded decimal processor with selective output formatting Feb 9, 1984 Issued
Menu