Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2286572 [patent_doc_number] => 04623979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-18 [patent_title] => 'Method and calculator for determining offset and angularity of coupled shafts' [patent_app_type] => 1 [patent_app_number] => 6/575343 [patent_app_country] => US [patent_app_date] => 1984-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5766 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/623/04623979.pdf [firstpage_image] =>[orig_patent_app_number] => 575343 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/575343
Method and calculator for determining offset and angularity of coupled shafts Jan 30, 1984 Issued
Array ( [id] => 2164180 [patent_doc_number] => 04554640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-19 [patent_title] => 'Programmable array logic circuit with shared product terms' [patent_app_type] => 1 [patent_app_number] => 6/575845 [patent_app_country] => US [patent_app_date] => 1984-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1800 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/554/04554640.pdf [firstpage_image] =>[orig_patent_app_number] => 575845 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/575845
Programmable array logic circuit with shared product terms Jan 29, 1984 Issued
Array ( [id] => 2238109 [patent_doc_number] => 04601007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-15 [patent_title] => 'Full adder' [patent_app_type] => 1 [patent_app_number] => 6/573718 [patent_app_country] => US [patent_app_date] => 1984-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3198 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 687 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/601/04601007.pdf [firstpage_image] =>[orig_patent_app_number] => 573718 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/573718
Full adder Jan 24, 1984 Issued
Array ( [id] => 2225106 [patent_doc_number] => 04631695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-23 [patent_title] => 'Detector of predetermined patterns of encoded data signals' [patent_app_type] => 1 [patent_app_number] => 6/573899 [patent_app_country] => US [patent_app_date] => 1984-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2455 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/631/04631695.pdf [firstpage_image] =>[orig_patent_app_number] => 573899 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/573899
Detector of predetermined patterns of encoded data signals Jan 23, 1984 Issued
Array ( [id] => 2349624 [patent_doc_number] => 04641259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-03 [patent_title] => 'Adaptive signal processing array with suppession of coherent and non-coherent interferring signals' [patent_app_type] => 1 [patent_app_number] => 6/572997 [patent_app_country] => US [patent_app_date] => 1984-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3723 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/641/04641259.pdf [firstpage_image] =>[orig_patent_app_number] => 572997 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/572997
Adaptive signal processing array with suppession of coherent and non-coherent interferring signals Jan 22, 1984 Issued
Array ( [id] => 2221092 [patent_doc_number] => 04615026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-30 [patent_title] => 'Digital FIR filters with enhanced tap weight resolution' [patent_app_type] => 1 [patent_app_number] => 6/572442 [patent_app_country] => US [patent_app_date] => 1984-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2395 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/615/04615026.pdf [firstpage_image] =>[orig_patent_app_number] => 572442 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/572442
Digital FIR filters with enhanced tap weight resolution Jan 19, 1984 Issued
Array ( [id] => 2211849 [patent_doc_number] => 04493081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-08 [patent_title] => 'Dynamic memory with error correction on refresh' [patent_app_type] => 1 [patent_app_number] => 6/569924 [patent_app_country] => US [patent_app_date] => 1984-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 17197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/493/04493081.pdf [firstpage_image] =>[orig_patent_app_number] => 569924 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/569924
Dynamic memory with error correction on refresh Jan 10, 1984 Issued
06/567830 FLOATING POINT CONDITION CODE GENERATION Jan 2, 1984 Abandoned
Array ( [id] => 2272939 [patent_doc_number] => 04612626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-16 [patent_title] => 'Method of performing real input fast fourier transforms simultaneously on two data streams' [patent_app_type] => 1 [patent_app_number] => 6/565991 [patent_app_country] => US [patent_app_date] => 1983-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2723 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/612/04612626.pdf [firstpage_image] =>[orig_patent_app_number] => 565991 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/565991
Method of performing real input fast fourier transforms simultaneously on two data streams Dec 26, 1983 Issued
Array ( [id] => 2286618 [patent_doc_number] => 04620293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-10-28 [patent_title] => 'Optical matrix multiplier' [patent_app_type] => 1 [patent_app_number] => 6/565062 [patent_app_country] => US [patent_app_date] => 1983-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2855 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/620/04620293.pdf [firstpage_image] =>[orig_patent_app_number] => 565062 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/565062
Optical matrix multiplier Dec 22, 1983 Issued
Array ( [id] => 2260575 [patent_doc_number] => 04590584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-20 [patent_title] => 'Method and system for processing exponents in floating-point multiplication' [patent_app_type] => 1 [patent_app_number] => 6/562736 [patent_app_country] => US [patent_app_date] => 1983-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2762 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/590/04590584.pdf [firstpage_image] =>[orig_patent_app_number] => 562736 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/562736
Method and system for processing exponents in floating-point multiplication Dec 18, 1983 Issued
Array ( [id] => 2223070 [patent_doc_number] => 04621324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-04 [patent_title] => 'Processor for carrying out vector operation wherein the same vector element is used repeatedly in succession' [patent_app_type] => 1 [patent_app_number] => 6/562224 [patent_app_country] => US [patent_app_date] => 1983-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3231 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/621/04621324.pdf [firstpage_image] =>[orig_patent_app_number] => 562224 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/562224
Processor for carrying out vector operation wherein the same vector element is used repeatedly in succession Dec 15, 1983 Issued
Array ( [id] => 2272951 [patent_doc_number] => 04612627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-16 [patent_title] => 'Digital signal composing circuit for cross-fade signal processing' [patent_app_type] => 1 [patent_app_number] => 6/560956 [patent_app_country] => US [patent_app_date] => 1983-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 34 [patent_no_of_words] => 5460 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/612/04612627.pdf [firstpage_image] =>[orig_patent_app_number] => 560956 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/560956
Digital signal composing circuit for cross-fade signal processing Dec 12, 1983 Issued
Array ( [id] => 2188228 [patent_doc_number] => 04504921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-12 [patent_title] => 'Multi-channel test system using optical waveguide modulators' [patent_app_type] => 1 [patent_app_number] => 6/560271 [patent_app_country] => US [patent_app_date] => 1983-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2270 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/504/04504921.pdf [firstpage_image] =>[orig_patent_app_number] => 560271 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/560271
Multi-channel test system using optical waveguide modulators Dec 11, 1983 Issued
Array ( [id] => 2138644 [patent_doc_number] => 04551814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-05 [patent_title] => 'Functionally redundant logic network architectures' [patent_app_type] => 1 [patent_app_number] => 6/560109 [patent_app_country] => US [patent_app_date] => 1983-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7942 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/551/04551814.pdf [firstpage_image] =>[orig_patent_app_number] => 560109 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/560109
Functionally redundant logic network architectures Dec 11, 1983 Issued
Array ( [id] => 2203627 [patent_doc_number] => 04503510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-05 [patent_title] => 'Method and apparatus for digital data compression' [patent_app_type] => 1 [patent_app_number] => 6/557968 [patent_app_country] => US [patent_app_date] => 1983-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7570 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/503/04503510.pdf [firstpage_image] =>[orig_patent_app_number] => 557968 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/557968
Method and apparatus for digital data compression Dec 4, 1983 Issued
Array ( [id] => 2132164 [patent_doc_number] => 04490807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-25 [patent_title] => 'Arithmetic device for concurrently summing two series of products from two sets of operands' [patent_app_type] => 1 [patent_app_number] => 6/556760 [patent_app_country] => US [patent_app_date] => 1983-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4043 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/490/04490807.pdf [firstpage_image] =>[orig_patent_app_number] => 556760 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/556760
Arithmetic device for concurrently summing two series of products from two sets of operands Nov 30, 1983 Issued
Array ( [id] => 2331598 [patent_doc_number] => 04636972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-13 [patent_title] => 'Method and apparatus for digital filtering' [patent_app_type] => 1 [patent_app_number] => 6/555261 [patent_app_country] => US [patent_app_date] => 1983-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6766 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/636/04636972.pdf [firstpage_image] =>[orig_patent_app_number] => 555261 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/555261
Method and apparatus for digital filtering Nov 24, 1983 Issued
Array ( [id] => 2162811 [patent_doc_number] => 04510603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-04-09 [patent_title] => 'Testing system for reliable access times in ROM semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 6/555441 [patent_app_country] => US [patent_app_date] => 1983-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6867 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/510/04510603.pdf [firstpage_image] =>[orig_patent_app_number] => 555441 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/555441
Testing system for reliable access times in ROM semiconductor memories Nov 24, 1983 Issued
Array ( [id] => 2283450 [patent_doc_number] => 04607343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-19 [patent_title] => 'Apparatus and method for performing division with an extended range of variables' [patent_app_type] => 1 [patent_app_number] => 6/555245 [patent_app_country] => US [patent_app_date] => 1983-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2688 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/607/04607343.pdf [firstpage_image] =>[orig_patent_app_number] => 555245 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/555245
Apparatus and method for performing division with an extended range of variables Nov 24, 1983 Issued
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