Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1890888 [patent_doc_number] => 04281390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-28 [patent_title] => 'Programmable calculator including means for performing computed and uncomputed relative branching during program execution' [patent_app_type] => 1 [patent_app_number] => 6/051581 [patent_app_country] => US [patent_app_date] => 1979-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13232 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/281/04281390.pdf [firstpage_image] =>[orig_patent_app_number] => 051581 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/051581
Programmable calculator including means for performing computed and uncomputed relative branching during program execution Jun 24, 1979 Issued
Array ( [id] => 1900567 [patent_doc_number] => 04263660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-21 [patent_title] => 'Expandable arithmetic logic unit' [patent_app_type] => 1 [patent_app_number] => 6/050382 [patent_app_country] => US [patent_app_date] => 1979-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 3286 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/263/04263660.pdf [firstpage_image] =>[orig_patent_app_number] => 050382 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/050382
Expandable arithmetic logic unit Jun 19, 1979 Issued
Array ( [id] => 1907112 [patent_doc_number] => 04302816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-11-24 [patent_title] => 'Key input control apparatus' [patent_app_type] => 1 [patent_app_number] => 6/050512 [patent_app_country] => US [patent_app_date] => 1979-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5446 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/302/04302816.pdf [firstpage_image] =>[orig_patent_app_number] => 050512 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/050512
Key input control apparatus Jun 19, 1979 Issued
Array ( [id] => 1901072 [patent_doc_number] => 04293921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-10-06 [patent_title] => 'Method and signal processor for frequency analysis of time domain signals' [patent_app_type] => 1 [patent_app_number] => 6/048810 [patent_app_country] => US [patent_app_date] => 1979-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 14924 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/293/04293921.pdf [firstpage_image] =>[orig_patent_app_number] => 048810 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/048810
Method and signal processor for frequency analysis of time domain signals Jun 14, 1979 Issued
Array ( [id] => 1897262 [patent_doc_number] => 04282582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-08-04 [patent_title] => 'Floating point processor architecture which performs subtraction with reduced number of guard bits' [patent_app_type] => 1 [patent_app_number] => 6/045218 [patent_app_country] => US [patent_app_date] => 1979-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2472 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/282/04282582.pdf [firstpage_image] =>[orig_patent_app_number] => 045218 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/045218
Floating point processor architecture which performs subtraction with reduced number of guard bits Jun 3, 1979 Issued
Array ( [id] => 1917132 [patent_doc_number] => 04308616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-12-29 [patent_title] => 'Structure for physical fault simulation of digital logic' [patent_app_type] => 1 [patent_app_number] => 6/043506 [patent_app_country] => US [patent_app_date] => 1979-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2682 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/308/04308616.pdf [firstpage_image] =>[orig_patent_app_number] => 043506 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/043506
Structure for physical fault simulation of digital logic May 28, 1979 Issued
Array ( [id] => 1915240 [patent_doc_number] => 04271522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-02 [patent_title] => 'Method of and apparatus for determining errors read from a magnetic recording medium' [patent_app_type] => 1 [patent_app_number] => 6/042299 [patent_app_country] => US [patent_app_date] => 1979-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 12251 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/271/04271522.pdf [firstpage_image] =>[orig_patent_app_number] => 042299 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/042299
Method of and apparatus for determining errors read from a magnetic recording medium May 24, 1979 Issued
Array ( [id] => 1903628 [patent_doc_number] => 04276608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-30 [patent_title] => 'Fibonacci p-code parallel adder' [patent_app_type] => 1 [patent_app_number] => 6/038930 [patent_app_country] => US [patent_app_date] => 1979-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4858 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 512 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/276/04276608.pdf [firstpage_image] =>[orig_patent_app_number] => 038930 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/038930
Fibonacci p-code parallel adder May 13, 1979 Issued
Array ( [id] => 1903623 [patent_doc_number] => 04276607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-30 [patent_title] => 'Multiplier circuit which detects and skips over trailing zeros' [patent_app_type] => 1 [patent_app_number] => 6/028214 [patent_app_country] => US [patent_app_date] => 1979-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4583 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/276/04276607.pdf [firstpage_image] =>[orig_patent_app_number] => 028214 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/028214
Multiplier circuit which detects and skips over trailing zeros Apr 8, 1979 Issued
Array ( [id] => 1912621 [patent_doc_number] => 04278850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-14 [patent_title] => 'Monitoring system for optical transmission line repeaters' [patent_app_type] => 1 [patent_app_number] => 6/028312 [patent_app_country] => US [patent_app_date] => 1979-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3280 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/278/04278850.pdf [firstpage_image] =>[orig_patent_app_number] => 028312 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/028312
Monitoring system for optical transmission line repeaters Apr 8, 1979 Issued
Array ( [id] => 1872476 [patent_doc_number] => 04253147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-02-24 [patent_title] => 'Memory unit with pipelined cycle of operations' [patent_app_type] => 1 [patent_app_number] => 6/028621 [patent_app_country] => US [patent_app_date] => 1979-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5078 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/253/04253147.pdf [firstpage_image] =>[orig_patent_app_number] => 028621 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/028621
Memory unit with pipelined cycle of operations Apr 8, 1979 Issued
Array ( [id] => 1900557 [patent_doc_number] => 04263658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-04-21 [patent_title] => 'Electronic apparatus capable of storing operational sequence' [patent_app_type] => 1 [patent_app_number] => 6/022142 [patent_app_country] => US [patent_app_date] => 1979-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1406 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/263/04263658.pdf [firstpage_image] =>[orig_patent_app_number] => 022142 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/022142
Electronic apparatus capable of storing operational sequence Mar 19, 1979 Issued
Array ( [id] => 1927998 [patent_doc_number] => 04272827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-09 [patent_title] => 'Division processing method system having 2N-bit precision' [patent_app_type] => 1 [patent_app_number] => 6/021011 [patent_app_country] => US [patent_app_date] => 1979-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9850 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/272/04272827.pdf [firstpage_image] =>[orig_patent_app_number] => 021011 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/021011
Division processing method system having 2N-bit precision Mar 15, 1979 Issued
Array ( [id] => 1910753 [patent_doc_number] => 04290102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-09-15 [patent_title] => 'Data processing system with read operation splitting' [patent_app_type] => 1 [patent_app_number] => 5/954566 [patent_app_country] => US [patent_app_date] => 1978-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 18733 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/290/04290102.pdf [firstpage_image] =>[orig_patent_app_number] => 954566 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/954566
Data processing system with read operation splitting Oct 24, 1978 Issued
Array ( [id] => 2042942 [patent_doc_number] => 04413326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-01 [patent_title] => 'Floating point division control' [patent_app_type] => 1 [patent_app_number] => 5/952567 [patent_app_country] => US [patent_app_date] => 1978-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3009 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/413/04413326.pdf [firstpage_image] =>[orig_patent_app_number] => 952567 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/952567
Floating point division control Oct 17, 1978 Issued
Array ( [id] => 3366657 [patent_doc_number] => 04224678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1980-09-23 [patent_title] => 'Method and apparatus for implementing a processor based on the rationalized Haar transform for the purpose of real time compression of video data' [patent_app_type] => 1 [patent_app_number] => 5/673799 [patent_app_country] => US [patent_app_date] => 1976-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5344 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/224/04224678.pdf [firstpage_image] =>[orig_patent_app_number] => 673799 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/673799
Method and apparatus for implementing a processor based on the rationalized Haar transform for the purpose of real time compression of video data Apr 4, 1976 Issued
Array ( [id] => 3130404 [patent_doc_number] => 05381357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Complex adaptive fir filter' [patent_app_type] => 1 [patent_app_number] => 8/068932 [patent_app_country] => US [patent_app_date] => 1903-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8390 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381357.pdf [firstpage_image] =>[orig_patent_app_number] => 068932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/068932
Complex adaptive fir filter May 27, 1903 Issued
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