Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9744704 [patent_doc_number] => 20140280423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD AND SYSTEM OF IMPROVED REED-SOLOMON DECODING' [patent_app_type] => utility [patent_app_number] => 13/842651 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842651
Method and system of improved reed-solomon decoding Mar 14, 2013 Issued
Array ( [id] => 10157424 [patent_doc_number] => 09189200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Multiple-precision processing block in a programmable integrated circuit device' [patent_app_type] => utility [patent_app_number] => 13/829729 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6846 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829729 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829729
Multiple-precision processing block in a programmable integrated circuit device Mar 13, 2013 Issued
Array ( [id] => 9744689 [patent_doc_number] => 20140280407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'VECTOR PROCESSING CARRY-SAVE ACCUMULATORS EMPLOYING REDUNDANT CARRY-SAVE FORMAT TO REDUCE CARRY PROPAGATION, AND RELATED VECTOR PROCESSORS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/798618 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16379 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/798618
VECTOR PROCESSING CARRY-SAVE ACCUMULATORS EMPLOYING REDUNDANT CARRY-SAVE FORMAT TO REDUCE CARRY PROPAGATION, AND RELATED VECTOR PROCESSORS, SYSTEMS, AND METHODS Mar 12, 2013
Array ( [id] => 10137666 [patent_doc_number] => 09170985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-27 [patent_title] => 'Bidirectional fast fourier transform in an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 13/802505 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11098 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802505 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802505
Bidirectional fast fourier transform in an integrated circuit device Mar 12, 2013 Issued
Array ( [id] => 8929781 [patent_doc_number] => 20130185541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'BITSTREAM BUFFER MANIPULATION WITH A SIMD MERGE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/788899 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788899
Bitstream buffer manipulation with a SIMD merge instruction Mar 6, 2013 Issued
Array ( [id] => 11186441 [patent_doc_number] => 09417842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Idempotent representation of numbers in extensible languages' [patent_app_type] => utility [patent_app_number] => 14/006071 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9775 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14006071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/006071
Idempotent representation of numbers in extensible languages Feb 28, 2013 Issued
Array ( [id] => 9296702 [patent_doc_number] => 20140040336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'METHOD OF ENTROPY DISTRIBUTION ON A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/778715 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6423 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13778715 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/778715
Method of entropy distribution on a parallel computer Feb 26, 2013 Issued
Array ( [id] => 9973967 [patent_doc_number] => 09021002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays' [patent_app_type] => utility [patent_app_number] => 13/760012 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5103 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760012
Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays Feb 4, 2013 Issued
Array ( [id] => 10530441 [patent_doc_number] => 09256577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Apparatuses and related methods for overflow detection and clamping with parallel operand processing' [patent_app_type] => utility [patent_app_number] => 13/758577 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3507 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758577
Apparatuses and related methods for overflow detection and clamping with parallel operand processing Feb 3, 2013 Issued
Array ( [id] => 10137708 [patent_doc_number] => 09171029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Performing batches of selective assignments in a vector friendly manner' [patent_app_type] => utility [patent_app_number] => 13/756438 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5490 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756438
Performing batches of selective assignments in a vector friendly manner Jan 30, 2013 Issued
13/754457 ULTRA HIGH SPEED RANDOM NUMBER GENERATORS Jan 29, 2013 Abandoned
Array ( [id] => 8855445 [patent_doc_number] => 20130145120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'Bitstream Buffer Manipulation With A SIMD Merge Instruction' [patent_app_type] => utility [patent_app_number] => 13/752953 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13961 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752953
Bitstream buffer manipulation with a SIMD merge instruction Jan 28, 2013 Issued
Array ( [id] => 10137495 [patent_doc_number] => 09170815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Bitstream buffer manipulation with a SIMD merge instruction' [patent_app_type] => utility [patent_app_number] => 13/752916 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13962 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752916
Bitstream buffer manipulation with a SIMD merge instruction Jan 28, 2013 Issued
Array ( [id] => 8855451 [patent_doc_number] => 20130145125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'Bitstream Buffer Manipulation With A SIMD Merge Instruction' [patent_app_type] => utility [patent_app_number] => 13/752987 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13961 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752987 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752987
Bitstream buffer manipulation with a SIMD merge instruction Jan 28, 2013 Issued
Array ( [id] => 10117535 [patent_doc_number] => 09152420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Bitstream buffer manipulation with a SIMD merge instruction' [patent_app_type] => utility [patent_app_number] => 13/753050 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13961 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753050
Bitstream buffer manipulation with a SIMD merge instruction Jan 28, 2013 Issued
Array ( [id] => 10027790 [patent_doc_number] => 09069691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Calculation method and computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 13/746390 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9718 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/746390
Calculation method and computer-readable recording medium Jan 21, 2013 Issued
Array ( [id] => 9604572 [patent_doc_number] => 20140201253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'Delay Device, Method, and Random Number Generator Using the Same' [patent_app_type] => utility [patent_app_number] => 13/742357 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6550 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/742357
Delay device, method, and random number generator using the same Jan 15, 2013 Issued
Array ( [id] => 10131124 [patent_doc_number] => 09164959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-20 [patent_title] => 'Discrete fourier transform calculation method and apparatus' [patent_app_type] => utility [patent_app_number] => 13/741141 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741141
Discrete fourier transform calculation method and apparatus Jan 13, 2013 Issued
Array ( [id] => 9070790 [patent_doc_number] => 20130262546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'ARITHMETIC CIRCUIT AND ARITHMETIC METHOD' [patent_app_type] => utility [patent_app_number] => 13/736343 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8235 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736343
ARITHMETIC CIRCUIT AND ARITHMETIC METHOD Jan 7, 2013 Abandoned
Array ( [id] => 9598900 [patent_doc_number] => 20140195581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'FIXED POINT DIVISION CIRCUIT UTILIZING FLOATING POINT ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/736677 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4092 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736677
FIXED POINT DIVISION CIRCUIT UTILIZING FLOATING POINT ARCHITECTURE Jan 7, 2013 Abandoned
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