David H. Malzahn

Array ( [id] => 47259 [patent_doc_number] => 07783693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Reconfigurable circuit' [patent_app_type] => utility [patent_app_number] => 11/442971 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783693.pdf [firstpage_image] =>[orig_patent_app_number] => 11442971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 192790 [patent_doc_number] => 07644116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Digital implementation of fractional exponentiation' [patent_app_type] => utility [patent_app_number] => 11/421425 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4741 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644116.pdf [firstpage_image] =>[orig_patent_app_number] => 11421425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5007151 [patent_doc_number] => 20070277628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Systems and methods for electronic dive table planner' [patent_app_type] => utility [patent_app_number] => 11/444144 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6892 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277628.pdf [firstpage_image] =>[orig_patent_app_number] => 11444144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4976371 [patent_doc_number] => 20070217602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for fast quotient guess and congruencies manipulation' [patent_app_type] => utility [patent_app_number] => 11/442922 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1565 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217602.pdf [firstpage_image] =>[orig_patent_app_number] => 11442922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5689754 [patent_doc_number] => 20060288069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Digital signal processing circuit having a SIMD circuit' [patent_app_type] => utility [patent_app_number] => 11/433331 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20060288069.pdf [firstpage_image] =>[orig_patent_app_number] => 11433331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861387 [patent_doc_number] => 20060230096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Digital signal processing circuit having an adder circuit with carry-outs' [patent_app_type] => utility [patent_app_number] => 11/433517 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230096.pdf [firstpage_image] =>[orig_patent_app_number] => 11433517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861385 [patent_doc_number] => 20060230094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Digital signal processing circuit having input register blocks' [patent_app_type] => utility [patent_app_number] => 11/432823 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230094.pdf [firstpage_image] =>[orig_patent_app_number] => 11432823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861381 [patent_doc_number] => 20060230093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Digital signal processing circuit having a pattern detector circuit for convergent rounding' [patent_app_type] => utility [patent_app_number] => 11/432847 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230093.pdf [firstpage_image] =>[orig_patent_app_number] => 11432847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4448790 [patent_doc_number] => 07865542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Digital signal processing block having a wide multiplexer' [patent_app_type] => utility [patent_app_number] => 11/433120 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 26269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865542.pdf [firstpage_image] =>[orig_patent_app_number] => 11433120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532420 [patent_doc_number] => 07844653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Digital signal processing circuit having a pre-adder circuit' [patent_app_type] => utility [patent_app_number] => 11/432848 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 26454 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844653.pdf [firstpage_image] =>[orig_patent_app_number] => 11432848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5047396 [patent_doc_number] => 20070266070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Split-radix FFT/IFFT processor' [patent_app_type] => utility [patent_app_number] => 11/432355 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2910 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266070.pdf [firstpage_image] =>[orig_patent_app_number] => 11432355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861380 [patent_doc_number] => 20060230092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Architectural floorplan for a digital signal processing circuit' [patent_app_type] => utility [patent_app_number] => 11/433369 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230092.pdf [firstpage_image] =>[orig_patent_app_number] => 11433369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4585213 [patent_doc_number] => 07849119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Digital signal processing circuit having a pattern detector circuit' [patent_app_type] => utility [patent_app_number] => 11/432846 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 26488 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849119.pdf [firstpage_image] =>[orig_patent_app_number] => 11432846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5689755 [patent_doc_number] => 20060288070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Digital signal processing circuit having a pattern circuit for determining termination conditions' [patent_app_type] => utility [patent_app_number] => 11/433332 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 26642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20060288070.pdf [firstpage_image] =>[orig_patent_app_number] => 11433332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4580085 [patent_doc_number] => 07840630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Arithmetic logic unit circuit' [patent_app_type] => utility [patent_app_number] => 11/433333 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 26556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840630.pdf [firstpage_image] =>[orig_patent_app_number] => 11433333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7593844 [patent_doc_number] => 07627623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Inverse modified discrete cosine transform (IMDCT) co-processor and audio decoder having the same' [patent_app_type] => utility [patent_app_number] => 11/432100 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2985 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/627/07627623.pdf [firstpage_image] =>[orig_patent_app_number] => 11432100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166421 [patent_doc_number] => 07672989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Large number multiplication method and device' [patent_app_type] => utility [patent_app_number] => 11/429190 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4168 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/672/07672989.pdf [firstpage_image] =>[orig_patent_app_number] => 11429190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7591531 [patent_doc_number] => 07653676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Efficient mapping of FFT to a reconfigurable parallel and pipeline data flow machine' [patent_app_type] => utility [patent_app_number] => 11/429068 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7431 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653676.pdf [firstpage_image] =>[orig_patent_app_number] => 11429068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5522983 [patent_doc_number] => 20090030964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'MATRIX OPERATION DEVICE' [patent_app_type] => utility [patent_app_number] => 11/915529 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10259 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20090030964.pdf [firstpage_image] =>[orig_patent_app_number] => 11915529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 107250 [patent_doc_number] => 07725512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Apparatus and method for performing multiple exclusive or operations using multiplication circuitry' [patent_app_type] => utility [patent_app_number] => 11/412694 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3222 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725512.pdf [firstpage_image] =>[orig_patent_app_number] => 11412694 [rel_patent_id] =>[rel_patent_doc_number] =>)