Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1164629 [patent_doc_number] => 06772182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Signal processing method for improving the signal-to-noise ratio of a noise-dominated channel and a matched-phase noise filter for implementing the same' [patent_app_type] => B1 [patent_app_number] => 08/757173 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4042 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772182.pdf [firstpage_image] =>[orig_patent_app_number] => 08757173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757173
Signal processing method for improving the signal-to-noise ratio of a noise-dominated channel and a matched-phase noise filter for implementing the same Nov 26, 1996 Issued
Array ( [id] => 3837521 [patent_doc_number] => 05784308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Binary subtraction device' [patent_app_type] => 1 [patent_app_number] => 8/751796 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 10785 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784308.pdf [firstpage_image] =>[orig_patent_app_number] => 751796 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751796
Binary subtraction device Nov 17, 1996 Issued
Array ( [id] => 7635044 [patent_doc_number] => 06381622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'System and method of expediting bit scan instructions' [patent_app_type] => B1 [patent_app_number] => 08/748123 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381622.pdf [firstpage_image] =>[orig_patent_app_number] => 08748123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748123
System and method of expediting bit scan instructions Nov 12, 1996 Issued
Array ( [id] => 3741078 [patent_doc_number] => 05636156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Adder with improved carry lookahead structure' [patent_app_type] => 1 [patent_app_number] => 8/730166 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2999 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636156.pdf [firstpage_image] =>[orig_patent_app_number] => 730166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730166
Adder with improved carry lookahead structure Oct 14, 1996 Issued
Array ( [id] => 4256342 [patent_doc_number] => 06144976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Hand-held data collection computer terminal having power management architecture including switchable multi-purpose input display screen' [patent_app_type] => 1 [patent_app_number] => 8/721820 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 16098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144976.pdf [firstpage_image] =>[orig_patent_app_number] => 721820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721820
Hand-held data collection computer terminal having power management architecture including switchable multi-purpose input display screen Sep 26, 1996 Issued
Array ( [id] => 3853265 [patent_doc_number] => 05847978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Processor and control method for performing proper saturation operation' [patent_app_type] => 1 [patent_app_number] => 8/721681 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8228 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847978.pdf [firstpage_image] =>[orig_patent_app_number] => 721681 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721681
Processor and control method for performing proper saturation operation Sep 26, 1996 Issued
Array ( [id] => 3802124 [patent_doc_number] => 05841683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Least significant bit and guard bit extractor' [patent_app_type] => 1 [patent_app_number] => 8/718272 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5437 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841683.pdf [firstpage_image] =>[orig_patent_app_number] => 718272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718272
Least significant bit and guard bit extractor Sep 19, 1996 Issued
Array ( [id] => 4010319 [patent_doc_number] => 05923574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Optimized, combined leading zeros counter and shifter' [patent_app_type] => 1 [patent_app_number] => 8/716591 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4409 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923574.pdf [firstpage_image] =>[orig_patent_app_number] => 716591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716591
Optimized, combined leading zeros counter and shifter Sep 17, 1996 Issued
Array ( [id] => 3882648 [patent_doc_number] => 05838599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method and apparatus for nonlinear exponential filtering of signals' [patent_app_type] => 1 [patent_app_number] => 8/713473 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5632 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838599.pdf [firstpage_image] =>[orig_patent_app_number] => 713473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713473
Method and apparatus for nonlinear exponential filtering of signals Sep 12, 1996 Issued
90/004363 MULTIFUNCTIONAL ARITHMETIC AND LOGIC UNIT IN SEMICONDUCTOR INTEGRATED CIRCUIT Sep 12, 1996 Issued
Array ( [id] => 4054296 [patent_doc_number] => 05912832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders' [patent_app_type] => 1 [patent_app_number] => 8/713822 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5941 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912832.pdf [firstpage_image] =>[orig_patent_app_number] => 713822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713822
Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders Sep 11, 1996 Issued
Array ( [id] => 3882701 [patent_doc_number] => 05838602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Fast carry generation adder having grouped carry muxes' [patent_app_type] => 1 [patent_app_number] => 8/712532 [patent_app_country] => US [patent_app_date] => 1996-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838602.pdf [firstpage_image] =>[orig_patent_app_number] => 712532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712532
Fast carry generation adder having grouped carry muxes Sep 10, 1996 Issued
Array ( [id] => 3986231 [patent_doc_number] => 05905660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Discrete cosine transform circuit for processing an 8.times.8 block and two 4.times.8 blocks' [patent_app_type] => 1 [patent_app_number] => 8/709841 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3608 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905660.pdf [firstpage_image] =>[orig_patent_app_number] => 709841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709841
Discrete cosine transform circuit for processing an 8.times.8 block and two 4.times.8 blocks Sep 9, 1996 Issued
Array ( [id] => 3988269 [patent_doc_number] => 05917732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus' [patent_app_type] => 1 [patent_app_number] => 8/724961 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 153 [patent_no_of_words] => 33640 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917732.pdf [firstpage_image] =>[orig_patent_app_number] => 724961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724961
Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus Sep 4, 1996 Issued
Array ( [id] => 3815882 [patent_doc_number] => 05854755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Clock frequency multiplication device' [patent_app_type] => 1 [patent_app_number] => 8/708681 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854755.pdf [firstpage_image] =>[orig_patent_app_number] => 708681 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708681
Clock frequency multiplication device Sep 4, 1996 Issued
Array ( [id] => 3774606 [patent_doc_number] => 05844825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Bidirectional shifter circuit' [patent_app_type] => 1 [patent_app_number] => 8/707222 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8871 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844825.pdf [firstpage_image] =>[orig_patent_app_number] => 707222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707222
Bidirectional shifter circuit Sep 2, 1996 Issued
Array ( [id] => 3732913 [patent_doc_number] => 05673213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Adaptive filter' [patent_app_type] => 1 [patent_app_number] => 8/704358 [patent_app_country] => US [patent_app_date] => 1996-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 11175 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673213.pdf [firstpage_image] =>[orig_patent_app_number] => 704358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/704358
Adaptive filter Aug 27, 1996 Issued
Array ( [id] => 3740738 [patent_doc_number] => 05666298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method for performing shift operations on packed data' [patent_app_type] => 1 [patent_app_number] => 8/701564 [patent_app_country] => US [patent_app_date] => 1996-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6964 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666298.pdf [firstpage_image] =>[orig_patent_app_number] => 701564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701564
Method for performing shift operations on packed data Aug 21, 1996 Issued
Array ( [id] => 3735857 [patent_doc_number] => RE035977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Look up table implementation of fast carry arithmetic and exclusive-or operations' [patent_app_type] => 2 [patent_app_number] => 8/700741 [patent_app_country] => US [patent_app_date] => 1996-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4019 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035977.pdf [firstpage_image] =>[orig_patent_app_number] => 700741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/700741
Look up table implementation of fast carry arithmetic and exclusive-or operations Aug 14, 1996 Issued
Array ( [id] => 4100454 [patent_doc_number] => 06018757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Zero detect for binary difference' [patent_app_type] => 1 [patent_app_number] => 8/695142 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11967 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018757.pdf [firstpage_image] =>[orig_patent_app_number] => 695142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/695142
Zero detect for binary difference Aug 7, 1996 Issued
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