Search

David H. Malzahn

Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786
Total Applications
3174
Issued Applications
2743
Pending Applications
60
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4077355 [patent_doc_number] => 05867415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Multiplication element including a wallace tree circuit having adders divided into high and low order adders' [patent_app_type] => 1 [patent_app_number] => 8/686072 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 13105 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867415.pdf [firstpage_image] =>[orig_patent_app_number] => 686072 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686072
Multiplication element including a wallace tree circuit having adders divided into high and low order adders Jul 23, 1996 Issued
Array ( [id] => 3970772 [patent_doc_number] => 05901074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Calculation data display devices and methods' [patent_app_type] => 1 [patent_app_number] => 8/681011 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5915 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901074.pdf [firstpage_image] =>[orig_patent_app_number] => 681011 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681011
Calculation data display devices and methods Jul 21, 1996 Issued
Array ( [id] => 3888385 [patent_doc_number] => 05764550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Arithmetic logic unit with improved critical path performance' [patent_app_type] => 1 [patent_app_number] => 8/681302 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 679 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764550.pdf [firstpage_image] =>[orig_patent_app_number] => 681302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681302
Arithmetic logic unit with improved critical path performance Jul 21, 1996 Issued
Array ( [id] => 3891900 [patent_doc_number] => 05805487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method and system for fast determination of sticky and guard bits' [patent_app_type] => 1 [patent_app_number] => 8/677843 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3338 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805487.pdf [firstpage_image] =>[orig_patent_app_number] => 677843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677843
Method and system for fast determination of sticky and guard bits Jul 11, 1996 Issued
Array ( [id] => 3788954 [patent_doc_number] => 05808924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Decimating IIR filter' [patent_app_type] => 1 [patent_app_number] => 8/676653 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4008 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808924.pdf [firstpage_image] =>[orig_patent_app_number] => 676653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/676653
Decimating IIR filter Jul 7, 1996 Issued
Array ( [id] => 3788405 [patent_doc_number] => 05808889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System and method for identifying and correcting computer operations involving two digit year dates' [patent_app_type] => 1 [patent_app_number] => 8/668513 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6047 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808889.pdf [firstpage_image] =>[orig_patent_app_number] => 668513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668513
System and method for identifying and correcting computer operations involving two digit year dates Jun 27, 1996 Issued
Array ( [id] => 3837493 [patent_doc_number] => 05784306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Parallel multiply accumulate array circuit' [patent_app_type] => 1 [patent_app_number] => 8/672613 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784306.pdf [firstpage_image] =>[orig_patent_app_number] => 672613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672613
Parallel multiply accumulate array circuit Jun 27, 1996 Issued
Array ( [id] => 3996494 [patent_doc_number] => 05961581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and circuit for detecting address limit violations in a microprocessor-based computer' [patent_app_type] => 1 [patent_app_number] => 8/671381 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5298 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961581.pdf [firstpage_image] =>[orig_patent_app_number] => 671381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671381
Method and circuit for detecting address limit violations in a microprocessor-based computer Jun 26, 1996 Issued
Array ( [id] => 3900463 [patent_doc_number] => 05777908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Comb filter with a smaller number of delay elements' [patent_app_type] => 1 [patent_app_number] => 8/668342 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 4221 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777908.pdf [firstpage_image] =>[orig_patent_app_number] => 668342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668342
Comb filter with a smaller number of delay elements Jun 25, 1996 Issued
Array ( [id] => 4054310 [patent_doc_number] => 05912833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Carry increment adder using clock phase' [patent_app_type] => 1 [patent_app_number] => 8/668363 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912833.pdf [firstpage_image] =>[orig_patent_app_number] => 668363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668363
Carry increment adder using clock phase Jun 25, 1996 Issued
Array ( [id] => 3783688 [patent_doc_number] => 05774387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Tracking filter' [patent_app_type] => 1 [patent_app_number] => 8/662803 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6060 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774387.pdf [firstpage_image] =>[orig_patent_app_number] => 662803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662803
Tracking filter Jun 11, 1996 Issued
Array ( [id] => 3791809 [patent_doc_number] => 05818745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Computer for performing non-restoring division' [patent_app_type] => 1 [patent_app_number] => 8/658933 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4157 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818745.pdf [firstpage_image] =>[orig_patent_app_number] => 658933 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658933
Computer for performing non-restoring division May 30, 1996 Issued
Array ( [id] => 4060922 [patent_doc_number] => 05870322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication' [patent_app_type] => 1 [patent_app_number] => 8/651482 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3036 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870322.pdf [firstpage_image] =>[orig_patent_app_number] => 651482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651482
Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication May 21, 1996 Issued
Array ( [id] => 3629500 [patent_doc_number] => 05642306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method and apparatus for a single instruction multiple data early-out zero-skip multiplier' [patent_app_type] => 1 [patent_app_number] => 8/645633 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3128 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642306.pdf [firstpage_image] =>[orig_patent_app_number] => 645633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645633
Method and apparatus for a single instruction multiple data early-out zero-skip multiplier May 14, 1996 Issued
Array ( [id] => 3891874 [patent_doc_number] => 05805485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Arithmetic unit and method for fourier transform' [patent_app_type] => 1 [patent_app_number] => 8/647763 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 11991 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805485.pdf [firstpage_image] =>[orig_patent_app_number] => 647763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647763
Arithmetic unit and method for fourier transform May 14, 1996 Issued
Array ( [id] => 3867457 [patent_doc_number] => 05706218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Random number generator' [patent_app_type] => 1 [patent_app_number] => 8/648553 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2257 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706218.pdf [firstpage_image] =>[orig_patent_app_number] => 648553 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648553
Random number generator May 14, 1996 Issued
08/564242 ULTRAFAST ADDER ARRANGEMENT May 12, 1996 Abandoned
Array ( [id] => 3788977 [patent_doc_number] => 05808925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Arithmetic unit and method for fourier transform' [patent_app_type] => 1 [patent_app_number] => 8/643233 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 15889 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808925.pdf [firstpage_image] =>[orig_patent_app_number] => 643233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643233
Arithmetic unit and method for fourier transform May 1, 1996 Issued
Array ( [id] => 3888369 [patent_doc_number] => 05764549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Fast floating point result alignment apparatus' [patent_app_type] => 1 [patent_app_number] => 8/639573 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3865 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764549.pdf [firstpage_image] =>[orig_patent_app_number] => 639573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639573
Fast floating point result alignment apparatus Apr 28, 1996 Issued
Array ( [id] => 3845277 [patent_doc_number] => 05815423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Parallel processing division circuit' [patent_app_type] => 1 [patent_app_number] => 8/638862 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5926 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815423.pdf [firstpage_image] =>[orig_patent_app_number] => 638862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638862
Parallel processing division circuit Apr 28, 1996 Issued
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