
David H. Malzahn
Examiner (ID: 17134, Phone: (571)272-3727 , Office: P/2182 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2193, 2306, 2301, 2787, 2182, 2121, 2302, 2124, 2183, 2307, 2786 |
| Total Applications | 3174 |
| Issued Applications | 2743 |
| Pending Applications | 60 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3844169
[patent_doc_number] => 05761101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Device and method for frequency generation'
[patent_app_type] => 1
[patent_app_number] => 8/570513
[patent_app_country] => US
[patent_app_date] => 1995-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2002
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761101.pdf
[firstpage_image] =>[orig_patent_app_number] => 570513
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/570513 | Device and method for frequency generation | Dec 10, 1995 | Issued |
Array
(
[id] => 3898638
[patent_doc_number] => 05724277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Background noise generating apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/568233
[patent_app_country] => US
[patent_app_date] => 1995-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7152
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/724/05724277.pdf
[firstpage_image] =>[orig_patent_app_number] => 568233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/568233 | Background noise generating apparatus | Dec 5, 1995 | Issued |
Array
(
[id] => 3830265
[patent_doc_number] => 05790440
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Apparatus for estimating filter coefficients'
[patent_app_type] => 1
[patent_app_number] => 8/567632
[patent_app_country] => US
[patent_app_date] => 1995-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 20105
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790440.pdf
[firstpage_image] =>[orig_patent_app_number] => 567632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567632 | Apparatus for estimating filter coefficients | Dec 4, 1995 | Issued |
Array
(
[id] => 3835877
[patent_doc_number] => 05732008
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Low-power high performance adder'
[patent_app_type] => 1
[patent_app_number] => 8/566962
[patent_app_country] => US
[patent_app_date] => 1995-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 3722
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 649
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/732/05732008.pdf
[firstpage_image] =>[orig_patent_app_number] => 566962
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566962 | Low-power high performance adder | Dec 3, 1995 | Issued |
Array
(
[id] => 3912549
[patent_doc_number] => 05751615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Implementation of a digital decimation filter and method'
[patent_app_type] => 1
[patent_app_number] => 8/557511
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8469
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751615.pdf
[firstpage_image] =>[orig_patent_app_number] => 557511
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557511 | Implementation of a digital decimation filter and method | Nov 13, 1995 | Issued |
Array
(
[id] => 3889940
[patent_doc_number] => 05729483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Implementation of a digital interpolation filter and method'
[patent_app_type] => 1
[patent_app_number] => 8/557592
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9311
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/729/05729483.pdf
[firstpage_image] =>[orig_patent_app_number] => 557592
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557592 | Implementation of a digital interpolation filter and method | Nov 13, 1995 | Issued |
Array
(
[id] => 3888439
[patent_doc_number] => 05764554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Method for the implementation of modular reduction according to the Montgomery method'
[patent_app_type] => 1
[patent_app_number] => 8/554781
[patent_app_country] => US
[patent_app_date] => 1995-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11711
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764554.pdf
[firstpage_image] =>[orig_patent_app_number] => 554781
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554781 | Method for the implementation of modular reduction according to the Montgomery method | Nov 6, 1995 | Issued |
Array
(
[id] => 3632711
[patent_doc_number] => 05594674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Code point update device in the arithmetic coding method'
[patent_app_type] => 1
[patent_app_number] => 8/549467
[patent_app_country] => US
[patent_app_date] => 1995-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 5429
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/594/05594674.pdf
[firstpage_image] =>[orig_patent_app_number] => 549467
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/549467 | Code point update device in the arithmetic coding method | Oct 26, 1995 | Issued |
Array
(
[id] => 3798341
[patent_doc_number] => 05737254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Symmetrical filtering apparatus and method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/549503
[patent_app_country] => US
[patent_app_date] => 1995-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 7221
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/737/05737254.pdf
[firstpage_image] =>[orig_patent_app_number] => 549503
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/549503 | Symmetrical filtering apparatus and method therefor | Oct 26, 1995 | Issued |
Array
(
[id] => 3891913
[patent_doc_number] => 05805488
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Method and structure for degrouping MPEG audio codes'
[patent_app_type] => 1
[patent_app_number] => 8/548930
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 11058
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805488.pdf
[firstpage_image] =>[orig_patent_app_number] => 548930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548930 | Method and structure for degrouping MPEG audio codes | Oct 25, 1995 | Issued |
Array
(
[id] => 3756465
[patent_doc_number] => 05717620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Improved-accuracy fast-Fourier-transform butterfly circuit'
[patent_app_type] => 1
[patent_app_number] => 8/547613
[patent_app_country] => US
[patent_app_date] => 1995-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3118
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717620.pdf
[firstpage_image] =>[orig_patent_app_number] => 547613
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/547613 | Improved-accuracy fast-Fourier-transform butterfly circuit | Oct 23, 1995 | Issued |
Array
(
[id] => 3557917
[patent_doc_number] => 05546333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Data processor having a data table for performing a dual function of alphanumeric notice and numerical calculations'
[patent_app_type] => 1
[patent_app_number] => 8/546260
[patent_app_country] => US
[patent_app_date] => 1995-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6421
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/546/05546333.pdf
[firstpage_image] =>[orig_patent_app_number] => 546260
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546260 | Data processor having a data table for performing a dual function of alphanumeric notice and numerical calculations | Oct 19, 1995 | Issued |
Array
(
[id] => 3891834
[patent_doc_number] => 05805482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Inverse discrete cosine transform processor having optimum input structure'
[patent_app_type] => 1
[patent_app_number] => 8/546471
[patent_app_country] => US
[patent_app_date] => 1995-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 37
[patent_no_of_words] => 11270
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805482.pdf
[firstpage_image] =>[orig_patent_app_number] => 546471
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546471 | Inverse discrete cosine transform processor having optimum input structure | Oct 19, 1995 | Issued |
Array
(
[id] => 3824559
[patent_doc_number] => 05812438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Arithmetic logic unit and method for numerical computations in galois fields'
[patent_app_type] => 1
[patent_app_number] => 8/542262
[patent_app_country] => US
[patent_app_date] => 1995-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 49
[patent_no_of_words] => 10139
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 428
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812438.pdf
[firstpage_image] =>[orig_patent_app_number] => 542262
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542262 | Arithmetic logic unit and method for numerical computations in galois fields | Oct 11, 1995 | Issued |
Array
(
[id] => 3824575
[patent_doc_number] => 05812439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Technique of incorporating floating point information into processor instructions'
[patent_app_type] => 1
[patent_app_number] => 8/541643
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4239
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812439.pdf
[firstpage_image] =>[orig_patent_app_number] => 541643
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541643 | Technique of incorporating floating point information into processor instructions | Oct 9, 1995 | Issued |
Array
(
[id] => 3912685
[patent_doc_number] => 05751622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Structure and method for signed multiplication using large multiplier having two embedded signed multipliers'
[patent_app_type] => 1
[patent_app_number] => 8/541563
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 8233
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751622.pdf
[firstpage_image] =>[orig_patent_app_number] => 541563
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541563 | Structure and method for signed multiplication using large multiplier having two embedded signed multipliers | Oct 9, 1995 | Issued |
Array
(
[id] => 3824544
[patent_doc_number] => 05812437
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Programmable logic unit for arithmetic, logic and equality functions'
[patent_app_type] => 1
[patent_app_number] => 8/541562
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2694
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812437.pdf
[firstpage_image] =>[orig_patent_app_number] => 541562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541562 | Programmable logic unit for arithmetic, logic and equality functions | Oct 9, 1995 | Issued |
Array
(
[id] => 1452018
[patent_doc_number] => 06370556
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Method and arrangement in a transposed digital FIR filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter'
[patent_app_type] => B1
[patent_app_number] => 08/522362
[patent_app_country] => US
[patent_app_date] => 1995-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2657
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/370/06370556.pdf
[firstpage_image] =>[orig_patent_app_number] => 08522362
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/522362 | Method and arrangement in a transposed digital FIR filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter | Sep 26, 1995 | Issued |
| 08/533811 | RESERVATION STATION INCLUDING ADDRESSABLE CONSTANT STORE FOR A FLOATING POINT PROCESSING UNIT | Sep 25, 1995 | Abandoned |
Array
(
[id] => 3892119
[patent_doc_number] => 05748516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Floating point processing unit with forced arithmetic results'
[patent_app_type] => 1
[patent_app_number] => 8/533812
[patent_app_country] => US
[patent_app_date] => 1995-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 10390
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748516.pdf
[firstpage_image] =>[orig_patent_app_number] => 533812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/533812 | Floating point processing unit with forced arithmetic results | Sep 25, 1995 | Issued |