Search

David J. Buttner

Examiner (ID: 4959)

Most Active Art Unit
1765
Art Unit(s)
1505, 1512, 1796, 1713, 1511, 1765, 1763, 1712, 1501
Total Applications
3220
Issued Applications
2139
Pending Applications
178
Abandoned Applications
916

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 741093 [patent_doc_number] => 07030020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method to shrink cell size in a split gate flash' [patent_app_type] => utility [patent_app_number] => 10/661746 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030020.pdf [firstpage_image] =>[orig_patent_app_number] => 10661746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/661746
Method to shrink cell size in a split gate flash Sep 11, 2003 Issued
Array ( [id] => 7127511 [patent_doc_number] => 20050059255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Wafer processing techniques with enhanced alignment' [patent_app_type] => utility [patent_app_number] => 10/661248 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5224 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059255.pdf [firstpage_image] =>[orig_patent_app_number] => 10661248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/661248
Wafer processing techniques with enhanced alignment Sep 11, 2003 Abandoned
Array ( [id] => 724525 [patent_doc_number] => 07045468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Isolated junction structure and method of manufacture' [patent_app_type] => utility [patent_app_number] => 10/646658 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2305 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045468.pdf [firstpage_image] =>[orig_patent_app_number] => 10646658 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646658
Isolated junction structure and method of manufacture Aug 20, 2003 Issued
Array ( [id] => 7289863 [patent_doc_number] => 20040110384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Detecting method for dry etching machine' [patent_app_type] => new [patent_app_number] => 10/604836 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3291 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110384.pdf [firstpage_image] =>[orig_patent_app_number] => 10604836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604836
Detecting method for dry etching machine Aug 20, 2003 Abandoned
Array ( [id] => 7353022 [patent_doc_number] => 20040048475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method for forming a storage node of a capacitor' [patent_app_type] => new [patent_app_number] => 10/641636 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4530 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20040048475.pdf [firstpage_image] =>[orig_patent_app_number] => 10641636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641636
Method for forming a storage node of a capacitor Aug 13, 2003 Issued
Array ( [id] => 753212 [patent_doc_number] => 07018560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Composition for polishing semiconductor layers' [patent_app_type] => utility [patent_app_number] => 10/634437 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7317 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018560.pdf [firstpage_image] =>[orig_patent_app_number] => 10634437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634437
Composition for polishing semiconductor layers Aug 4, 2003 Issued
Array ( [id] => 641782 [patent_doc_number] => 07122481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Sealing porous dielectrics with silane coupling reagents' [patent_app_type] => utility [patent_app_number] => 10/627838 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2445 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122481.pdf [firstpage_image] =>[orig_patent_app_number] => 10627838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627838
Sealing porous dielectrics with silane coupling reagents Jul 24, 2003 Issued
Array ( [id] => 7235712 [patent_doc_number] => 20040157464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Manufacturing method of electronic device having wiring connection structure' [patent_app_type] => new [patent_app_number] => 10/608028 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3409 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157464.pdf [firstpage_image] =>[orig_patent_app_number] => 10608028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608028
Manufacturing method of electronic device having wiring connection structure Jun 29, 2003 Abandoned
Array ( [id] => 741161 [patent_doc_number] => 07030031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material' [patent_app_type] => utility [patent_app_number] => 10/604056 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4560 [patent_no_of_claims] => 94 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030031.pdf [firstpage_image] =>[orig_patent_app_number] => 10604056 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604056
Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material Jun 23, 2003 Issued
Array ( [id] => 748329 [patent_doc_number] => 07022251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Methods for forming a conductor on a dielectric' [patent_app_type] => utility [patent_app_number] => 10/601042 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1640 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022251.pdf [firstpage_image] =>[orig_patent_app_number] => 10601042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/601042
Methods for forming a conductor on a dielectric Jun 18, 2003 Issued
Array ( [id] => 714244 [patent_doc_number] => 07052621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Bilayered metal hardmasks for use in Dual Damascene etch schemes' [patent_app_type] => utility [patent_app_number] => 10/461090 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3094 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052621.pdf [firstpage_image] =>[orig_patent_app_number] => 10461090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461090
Bilayered metal hardmasks for use in Dual Damascene etch schemes Jun 12, 2003 Issued
Array ( [id] => 7383782 [patent_doc_number] => 20040029386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method of patterning inter-metal dielectric layers' [patent_app_type] => new [patent_app_number] => 10/454488 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2997 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029386.pdf [firstpage_image] =>[orig_patent_app_number] => 10454488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454488
Method of patterning inter-metal dielectric layers Jun 4, 2003 Abandoned
Array ( [id] => 6699360 [patent_doc_number] => 20030222240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Piezoelectric ceramic production method and piezoelectric element production method' [patent_app_type] => new [patent_app_number] => 10/448212 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17833 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 30 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222240.pdf [firstpage_image] =>[orig_patent_app_number] => 10448212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448212
Piezoelectric ceramic production method and piezoelectric element production method May 29, 2003 Issued
Array ( [id] => 7409011 [patent_doc_number] => 20040106284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Signal layer for generating characteristic optical plasma emissions' [patent_app_type] => new [patent_app_number] => 10/447877 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4740 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106284.pdf [firstpage_image] =>[orig_patent_app_number] => 10447877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447877
Signal layer for generating characteristic optical plasma emissions May 28, 2003 Issued
Array ( [id] => 7471727 [patent_doc_number] => 20040121599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Simultaneous formation of device and backside contacts on wafers having a buried insulator layer' [patent_app_type] => new [patent_app_number] => 10/446974 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121599.pdf [firstpage_image] =>[orig_patent_app_number] => 10446974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446974
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer May 27, 2003 Issued
Array ( [id] => 7400818 [patent_doc_number] => 20040023505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method of removing ALF defects after pad etching process' [patent_app_type] => new [patent_app_number] => 10/442267 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1479 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023505.pdf [firstpage_image] =>[orig_patent_app_number] => 10442267 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442267
Method of removing ALF defects after pad etching process May 20, 2003 Abandoned
Array ( [id] => 709478 [patent_doc_number] => 07056448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method for forming circuit pattern' [patent_app_type] => utility [patent_app_number] => 10/441588 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7435 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/056/07056448.pdf [firstpage_image] =>[orig_patent_app_number] => 10441588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441588
Method for forming circuit pattern May 19, 2003 Issued
Array ( [id] => 735631 [patent_doc_number] => 07033519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Method of fabricating sub-micron structures in transparent dielectric materials' [patent_app_type] => utility [patent_app_number] => 10/431442 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8646 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033519.pdf [firstpage_image] =>[orig_patent_app_number] => 10431442 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431442
Method of fabricating sub-micron structures in transparent dielectric materials May 7, 2003 Issued
Array ( [id] => 754406 [patent_doc_number] => 07018933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method of forming a metal-insulator-metal capacitor' [patent_app_type] => utility [patent_app_number] => 10/426743 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018933.pdf [firstpage_image] =>[orig_patent_app_number] => 10426743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426743
Method of forming a metal-insulator-metal capacitor Apr 29, 2003 Issued
Array ( [id] => 749762 [patent_doc_number] => 07022611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Plasma in-situ treatment of chemically amplified resist' [patent_app_type] => utility [patent_app_number] => 10/426043 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6424 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022611.pdf [firstpage_image] =>[orig_patent_app_number] => 10426043 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426043
Plasma in-situ treatment of chemically amplified resist Apr 27, 2003 Issued
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