
David J. Goodwin
Examiner (ID: 414, Phone: (571)272-8451 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2817, 2818, 2822 |
| Total Applications | 1083 |
| Issued Applications | 702 |
| Pending Applications | 118 |
| Abandoned Applications | 297 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18919188
[patent_doc_number] => 11881477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-23
[patent_title] => Dummy poly layout for high density devices
[patent_app_type] => utility
[patent_app_number] => 16/902636
[patent_app_country] => US
[patent_app_date] => 2020-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 8032
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902636
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/902636 | Dummy poly layout for high density devices | Jun 15, 2020 | Issued |
Array
(
[id] => 16332484
[patent_doc_number] => 20200303450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => PIXELATED LED ARRAY WITH OPTICAL ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 16/894449
[patent_app_country] => US
[patent_app_date] => 2020-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2899
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16894449
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/894449 | Pixelated LED array with optical elements | Jun 4, 2020 | Issued |
Array
(
[id] => 18494237
[patent_doc_number] => 11699658
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Semiconductor device with metal interconnection
[patent_app_type] => utility
[patent_app_number] => 16/889467
[patent_app_country] => US
[patent_app_date] => 2020-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 11396
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889467
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/889467 | Semiconductor device with metal interconnection | May 31, 2020 | Issued |
Array
(
[id] => 16981593
[patent_doc_number] => 20210225830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS RELATED THERETO
[patent_app_type] => utility
[patent_app_number] => 16/883610
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883610
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883610 | Semiconductor devices and methods related thereto | May 25, 2020 | Issued |
Array
(
[id] => 19277330
[patent_doc_number] => 12027462
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Method and structure for determining blocking ability of copper diffusion blocking layer
[patent_app_type] => utility
[patent_app_number] => 16/961927
[patent_app_country] => US
[patent_app_date] => 2020-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4780
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961927
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/961927 | Method and structure for determining blocking ability of copper diffusion blocking layer | May 20, 2020 | Issued |
Array
(
[id] => 18608192
[patent_doc_number] => 11749670
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Power switch for backside power distribution
[patent_app_type] => utility
[patent_app_number] => 16/877256
[patent_app_country] => US
[patent_app_date] => 2020-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8606
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877256
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/877256 | Power switch for backside power distribution | May 17, 2020 | Issued |
Array
(
[id] => 17203559
[patent_doc_number] => 20210343654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-04
[patent_title] => SEMICONDUCTOR PACKAGE WITH AIR GAP AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/865909
[patent_app_country] => US
[patent_app_date] => 2020-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865909
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/865909 | Semiconductor package with air gap and manufacturing method thereof | May 3, 2020 | Issued |
Array
(
[id] => 16951768
[patent_doc_number] => 20210210460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => METHODS FOR MULTI-WAFER STACKING AND DICING
[patent_app_type] => utility
[patent_app_number] => 16/862298
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22616
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862298
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/862298 | Methods for multi-wafer stacking and dicing | Apr 28, 2020 | Issued |
Array
(
[id] => 16440644
[patent_doc_number] => 20200357971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/860040
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6360
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860040
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/860040 | Electronic device | Apr 26, 2020 | Issued |
Array
(
[id] => 16379354
[patent_doc_number] => 20200328197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/845712
[patent_app_country] => US
[patent_app_date] => 2020-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845712
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/845712 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THEREOF | Apr 9, 2020 | Abandoned |
Array
(
[id] => 16194438
[patent_doc_number] => 20200235287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-23
[patent_title] => ELECTRICAL CONTACT STRUCTURE AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/837045
[patent_app_country] => US
[patent_app_date] => 2020-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2958
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837045
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/837045 | Electrical contact structure and methods for forming the same | Mar 31, 2020 | Issued |
Array
(
[id] => 19046768
[patent_doc_number] => 11935888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Integrated circuit having fins crossing cell boundary
[patent_app_type] => utility
[patent_app_number] => 16/837497
[patent_app_country] => US
[patent_app_date] => 2020-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 13563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837497
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/837497 | Integrated circuit having fins crossing cell boundary | Mar 31, 2020 | Issued |
Array
(
[id] => 17130390
[patent_doc_number] => 20210305159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => MICROELECTRONIC DEVICE INTERFACE CONFIGURATIONS, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 16/832550
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832550
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/832550 | Microelectronic device interface configurations, and associated methods, devices, and systems | Mar 26, 2020 | Issued |
Array
(
[id] => 17493503
[patent_doc_number] => 11282819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Semiconductor device having chip-to-chip bonding structure
[patent_app_type] => utility
[patent_app_number] => 16/830124
[patent_app_country] => US
[patent_app_date] => 2020-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8142
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830124
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/830124 | Semiconductor device having chip-to-chip bonding structure | Mar 24, 2020 | Issued |
Array
(
[id] => 16560427
[patent_doc_number] => 20210005576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/822693
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7172
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822693
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/822693 | Semiconductor package | Mar 17, 2020 | Issued |
Array
(
[id] => 17115637
[patent_doc_number] => 20210296234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => INTERCONNECTION FABRIC FOR BURIED POWER DISTRIBUTION
[patent_app_type] => utility
[patent_app_number] => 16/822803
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822803
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/822803 | INTERCONNECTION FABRIC FOR BURIED POWER DISTRIBUTION | Mar 17, 2020 | Pending |
Array
(
[id] => 16715730
[patent_doc_number] => 20210082877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/803228
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803228
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/803228 | Semiconductor device and method for manufacturing the same | Feb 26, 2020 | Issued |
Array
(
[id] => 16715753
[patent_doc_number] => 20210082900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/798797
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798797
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/798797 | Method for manufacturing semiconductor device | Feb 23, 2020 | Issued |
Array
(
[id] => 16593923
[patent_doc_number] => 10903200
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-26
[patent_title] => Semiconductor device manufacturing method
[patent_app_type] => utility
[patent_app_number] => 16/793323
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3448
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793323
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793323 | Semiconductor device manufacturing method | Feb 17, 2020 | Issued |
Array
(
[id] => 18073736
[patent_doc_number] => 11532576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Semiconductor package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/787020
[patent_app_country] => US
[patent_app_date] => 2020-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 12375
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787020
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/787020 | Semiconductor package and manufacturing method thereof | Feb 10, 2020 | Issued |