Search

David J. Goodwin

Examiner (ID: 414, Phone: (571)272-8451 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2818, 2822
Total Applications
1083
Issued Applications
702
Pending Applications
118
Abandoned Applications
297

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15656845 [patent_doc_number] => 20200090953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/269960 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269960 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269960
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Feb 6, 2019 Abandoned
Array ( [id] => 16068087 [patent_doc_number] => 10693009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Structure of S/D contact and method of making same [patent_app_type] => utility [patent_app_number] => 16/266454 [patent_app_country] => US [patent_app_date] => 2019-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4795 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/266454
Structure of S/D contact and method of making same Feb 3, 2019 Issued
Array ( [id] => 16210415 [patent_doc_number] => 20200243405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ANISOTROPIC CONDUCTIVE FILM (ACF) FOR USE IN TESTING SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/261278 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261278
Anisotropic conductive film (ACF) for use in testing semiconductor packages Jan 28, 2019 Issued
Array ( [id] => 14414159 [patent_doc_number] => 20190172923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => Integrated Epitaxial Metal Electrodes [patent_app_type] => utility [patent_app_number] => 16/257707 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257707 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/257707
Integrated epitaxial metal electrodes Jan 24, 2019 Issued
Array ( [id] => 15139415 [patent_doc_number] => 10483193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Electrical connectivity for circuit applications [patent_app_type] => utility [patent_app_number] => 16/247941 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247941
Electrical connectivity for circuit applications Jan 14, 2019 Issued
Array ( [id] => 14350457 [patent_doc_number] => 20190157201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS [patent_app_type] => utility [patent_app_number] => 16/237782 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237782
Interconnect structures with fully aligned vias Jan 1, 2019 Issued
Array ( [id] => 16119973 [patent_doc_number] => 20200212009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => DIODE FOR USE IN TESTING SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/235859 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/235859
Diode for use in testing semiconductor packages Dec 27, 2018 Issued
Array ( [id] => 15519287 [patent_doc_number] => 10566237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Profile of through via protrusion in 3DIC interconnect [patent_app_type] => utility [patent_app_number] => 16/227928 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227928
Profile of through via protrusion in 3DIC interconnect Dec 19, 2018 Issued
Array ( [id] => 16035115 [patent_doc_number] => 10679990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Multi-fin device and method of making same [patent_app_type] => utility [patent_app_number] => 16/221897 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221897
Multi-fin device and method of making same Dec 16, 2018 Issued
Array ( [id] => 14164033 [patent_doc_number] => 20190109119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => Package Structures and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/206540 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206540
Package structures and methods of forming the same Nov 29, 2018 Issued
Array ( [id] => 19582584 [patent_doc_number] => 12148712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/275165 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4838 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17275165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/275165
Semiconductor device and method of manufacturing semiconductor device Nov 19, 2018 Issued
Array ( [id] => 17018336 [patent_doc_number] => 11087981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Poly-silicon layer and method of manufacturing the same, methods of manufacturing thin film transistor and array substrate [patent_app_type] => utility [patent_app_number] => 16/349780 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5097 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16349780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/349780
Poly-silicon layer and method of manufacturing the same, methods of manufacturing thin film transistor and array substrate Nov 6, 2018 Issued
Array ( [id] => 16418010 [patent_doc_number] => 10825912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Integrated epitaxial metal electrodes [patent_app_type] => utility [patent_app_number] => 16/178495 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 8427 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16178495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/178495
Integrated epitaxial metal electrodes Oct 31, 2018 Issued
Array ( [id] => 15348531 [patent_doc_number] => 20200012157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => METHOD AND APPARATUS FOR MANUFACTURING DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/329173 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16329173 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/329173
METHOD AND APPARATUS FOR MANUFACTURING DISPLAY PANEL Oct 14, 2018 Abandoned
Array ( [id] => 13909755 [patent_doc_number] => 20190044082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => LIQUID ORGANIC SEMICONDUCTOR MATERIAL [patent_app_type] => utility [patent_app_number] => 16/155444 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155444 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155444
LIQUID ORGANIC SEMICONDUCTOR MATERIAL Oct 8, 2018 Abandoned
Array ( [id] => 19243010 [patent_doc_number] => 12013442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => In-line detection of electrical fails on integrated circuits [patent_app_type] => utility [patent_app_number] => 16/147564 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6022 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147564
In-line detection of electrical fails on integrated circuits Sep 27, 2018 Issued
Array ( [id] => 17032900 [patent_doc_number] => 11094718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => TFT array substrate [patent_app_type] => utility [patent_app_number] => 16/319819 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6818 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 613 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16319819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/319819
TFT array substrate Sep 26, 2018 Issued
Array ( [id] => 13848179 [patent_doc_number] => 20190027574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => Metal Electrode With Tunable Work Functions [patent_app_type] => utility [patent_app_number] => 16/138629 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138629
Metal electrode with tunable work functions Sep 20, 2018 Issued
Array ( [id] => 17410199 [patent_doc_number] => 11251096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Wafer registration and overlay measurement systems and related methods [patent_app_type] => utility [patent_app_number] => 16/122106 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 18317 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122106
Wafer registration and overlay measurement systems and related methods Sep 4, 2018 Issued
Array ( [id] => 13832165 [patent_doc_number] => 20190019567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => TEST LINE LETTER FOR EMBEDDED NON-VOLATILE MEMORY TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 16/122104 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122104
Test line letter for embedded non-volatile memory technology Sep 4, 2018 Issued
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