
David J. Goodwin
Examiner (ID: 4085, Phone: (571)272-8451 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2818, 2822, 2817 |
| Total Applications | 1103 |
| Issued Applications | 710 |
| Pending Applications | 110 |
| Abandoned Applications | 301 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19349280
[patent_doc_number] => 20240258244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => METHODS FOR MECHANICAL SELF-ALIGNMENT AND SLIP-RESISTANCE IN BONDING SEMICONDUCTOR SUBSTRATES, AND SEMICONDUCTOR DEVICES COMPRISING MECHANICAL SELF-ALIGNMENT STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/403007
[patent_app_country] => US
[patent_app_date] => 2024-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3201
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403007
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/403007 | METHODS FOR MECHANICAL SELF-ALIGNMENT AND SLIP-RESISTANCE IN BONDING SEMICONDUCTOR SUBSTRATES, AND SEMICONDUCTOR DEVICES COMPRISING MECHANICAL SELF-ALIGNMENT STRUCTURES | Jan 2, 2024 | Pending |
Array
(
[id] => 19285822
[patent_doc_number] => 20240222299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/402021
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11650
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402021
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402021 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | Jan 1, 2024 | Pending |
Array
(
[id] => 19206093
[patent_doc_number] => 20240177992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => METHOD OF FORMING AN ORGANIC POLYMER COMPRISING POLYIMIDE
[patent_app_type] => utility
[patent_app_number] => 18/519172
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519172
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/519172 | METHOD OF FORMING AN ORGANIC POLYMER COMPRISING POLYIMIDE | Nov 26, 2023 | Pending |
Array
(
[id] => 19071101
[patent_doc_number] => 20240105527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/372232
[patent_app_country] => US
[patent_app_date] => 2023-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18372232
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/372232 | ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME | Sep 24, 2023 | Pending |
Array
(
[id] => 18865965
[patent_doc_number] => 20230420402
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/244462
[patent_app_country] => US
[patent_app_date] => 2023-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18244462
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/244462 | SEMICONDUCTOR PACKAGE | Sep 10, 2023 | Pending |
Array
(
[id] => 19546418
[patent_doc_number] => 20240363454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => CIRCUIT PROBING PAD DESIGN IN SCRIBE LINE STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR CHIP
[patent_app_type] => utility
[patent_app_number] => 18/239231
[patent_app_country] => US
[patent_app_date] => 2023-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239231
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/239231 | CIRCUIT PROBING PAD DESIGN IN SCRIBE LINE STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR CHIP | Aug 28, 2023 | Pending |
Array
(
[id] => 19022888
[patent_doc_number] => 20240079059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => HIGH VOLTAGE DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/238848
[patent_app_country] => US
[patent_app_date] => 2023-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6311
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238848
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/238848 | HIGH VOLTAGE DEVICE AND METHOD | Aug 27, 2023 | Pending |
Array
(
[id] => 19812453
[patent_doc_number] => 12243866
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Power switch for backside power distribution
[patent_app_type] => utility
[patent_app_number] => 18/361454
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8640
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361454
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361454 | Power switch for backside power distribution | Jul 27, 2023 | Issued |
Array
(
[id] => 19116382
[patent_doc_number] => 20240128132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
[patent_app_type] => utility
[patent_app_number] => 18/221803
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8880
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221803
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/221803 | SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING | Jul 12, 2023 | Pending |
Array
(
[id] => 19116384
[patent_doc_number] => 20240128134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
[patent_app_type] => utility
[patent_app_number] => 18/221797
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221797
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/221797 | SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING | Jul 12, 2023 | Pending |
Array
(
[id] => 18743365
[patent_doc_number] => 20230352353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/344857
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8087
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344857
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344857 | METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE | Jun 29, 2023 | Pending |
Array
(
[id] => 18743451
[patent_doc_number] => 20230352439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => Multi-Level Stacking of Wafers and Chips
[patent_app_type] => utility
[patent_app_number] => 18/338107
[patent_app_country] => US
[patent_app_date] => 2023-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338107
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/338107 | Multi-Level Stacking of Wafers and Chips | Jun 19, 2023 | Pending |
Array
(
[id] => 19286082
[patent_doc_number] => 20240222560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => MICRO LIGHT-EMITTING CHIP STRUCTURE AND MICRO DISPLAY STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/328190
[patent_app_country] => US
[patent_app_date] => 2023-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6437
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328190
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/328190 | MICRO LIGHT-EMITTING CHIP STRUCTURE AND MICRO DISPLAY STRUCTURE | Jun 1, 2023 | Pending |
Array
(
[id] => 18661399
[patent_doc_number] => 20230307413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => METHODS FOR MULTI-WAFER STACKING AND DICING
[patent_app_type] => utility
[patent_app_number] => 18/205364
[patent_app_country] => US
[patent_app_date] => 2023-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22630
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205364
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/205364 | METHODS FOR MULTI-WAFER STACKING AND DICING | Jun 1, 2023 | Pending |
Array
(
[id] => 18729360
[patent_doc_number] => 20230343656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME
[patent_app_type] => utility
[patent_app_number] => 18/197240
[patent_app_country] => US
[patent_app_date] => 2023-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197240
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/197240 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME | May 14, 2023 | Pending |
Array
(
[id] => 18615882
[patent_doc_number] => 20230282621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/316051
[patent_app_country] => US
[patent_app_date] => 2023-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316051
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/316051 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | May 10, 2023 | Pending |
Array
(
[id] => 19546417
[patent_doc_number] => 20240363453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => CIRCUIT PROBING PAD DESIGN IN SCRIBE LINE STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR CHIP
[patent_app_type] => utility
[patent_app_number] => 18/140085
[patent_app_country] => US
[patent_app_date] => 2023-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6327
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140085
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/140085 | CIRCUIT PROBING PAD DESIGN IN SCRIBE LINE STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR CHIP | Apr 26, 2023 | Pending |
Array
(
[id] => 18586152
[patent_doc_number] => 20230268417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/304137
[patent_app_country] => US
[patent_app_date] => 2023-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304137
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/304137 | Method for forming a semiconductor structure | Apr 19, 2023 | Issued |
Array
(
[id] => 18540878
[patent_doc_number] => 20230245989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => PRINTED CIRCUIT BOARD AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/132096
[patent_app_country] => US
[patent_app_date] => 2023-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10037
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132096
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/132096 | PRINTED CIRCUIT BOARD AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME | Apr 6, 2023 | Pending |
Array
(
[id] => 18906054
[patent_doc_number] => 20240021539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/117848
[patent_app_country] => US
[patent_app_date] => 2023-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8122
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117848
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/117848 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Mar 5, 2023 | Pending |