David J. Goodwin

Array ( [id] => 10378020 [patent_doc_number] => 20150263027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/483610 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703159 [patent_doc_number] => 20160049307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Patterning method for IC fabrication using 2-D layout decomposition and synthesis techniques' [patent_app_type] => utility [patent_app_number] => 14/121229 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2926 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14121229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10701619 [patent_doc_number] => 20160047766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'IMPRINTED THIN-FILM ELECTRONIC SENSOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/460578 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8553 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10492443 [patent_doc_number] => 20150377465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'DISPLAY DEVICE AND PROCESSING APPARATUS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/460656 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4611 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13132241 [patent_doc_number] => 10084060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Semiconductor structure and manufacturing method of the same [patent_app_type] => utility [patent_app_number] => 14/460535 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703217 [patent_doc_number] => 20160049364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS' [patent_app_type] => utility [patent_app_number] => 14/460435 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4988 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13893893 [patent_doc_number] => 10199502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Structure of S/D contact and method of making same [patent_app_type] => utility [patent_app_number] => 14/460438 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703256 [patent_doc_number] => 20160049403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'CMOS COMPATIBLE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/459403 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8539 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10351156 [patent_doc_number] => 20150236161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/459949 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703192 [patent_doc_number] => 20160049339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'BLOCK PATTERNING PROCESS FOR POST FIN' [patent_app_type] => utility [patent_app_number] => 14/459407 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5161 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703144 [patent_doc_number] => 20160049291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD OF FORMING THIN FILM OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/459644 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12969304 [patent_doc_number] => 09876008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Bandgap reference circuit [patent_app_type] => utility [patent_app_number] => 14/458994 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703254 [patent_doc_number] => 20160049401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'HYBRID CONTACTS FOR COMMONLY FABRICATED SEMICONDUCTOR DEVICES USING SAME METAL' [patent_app_type] => utility [patent_app_number] => 14/459005 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703341 [patent_doc_number] => 20160049488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'SEMICONDUCTOR GATE WITH WIDE TOP OR BOTTOM' [patent_app_type] => utility [patent_app_number] => 14/458941 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703147 [patent_doc_number] => 20160049294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Mixed Lithography Approach for E-Beam and Optical Exposure Using HSQ' [patent_app_type] => utility [patent_app_number] => 14/458887 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703237 [patent_doc_number] => 20160049384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA' [patent_app_type] => utility [patent_app_number] => 14/459144 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7905 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9697036 [patent_doc_number] => 20140246721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/274170 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 18870 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10252205 [patent_doc_number] => 20150137201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'HIGH DENSITY LINEAR CAPACITOR' [patent_app_type] => utility [patent_app_number] => 14/264620 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4442 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10427998 [patent_doc_number] => 20150313009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'THIN-FILM MULTI-LAYER MICRO-WIRE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/264499 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10413 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10426127 [patent_doc_number] => 20150311138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'TRANSISTORS WITH IMPROVED THERMAL CONDUCTIVITY' [patent_app_type] => utility [patent_app_number] => 14/264229 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4538 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264229 [rel_patent_id] =>[rel_patent_doc_number] =>)